mo.khairy.mo
Member level 2
hi all
what's the error in this vhdl code
if i need to port map some components depend on conditions how can i do it?
thanks in advance
what's the error in this vhdl code
Code:
when (opcode = addu) =>
I0 : int_2s_add_sub
PORT MAP (
clk => clk,
enable => '1',
rst => rst,
opa => opa,
opb => opb,
M => '0',
OVF => flags(5),
opc => opc
);
if i need to port map some components depend on conditions how can i do it?
thanks in advance