synchronous clock domain crossing

[kalyansumankv]

Hi all,
Can some help me in understanding what is "synchronous clock domain crossing",
what kind of problems we can face from the above, and what are the methods to avoid the same....

Thanks&Regards
Kalyansuman

 

[anantha_09]

**broken link removed**

https://www.asic-world.com/tidbits/clock_domain.html

 

[kalyansumankv]

Dear Anantha,
thanks a lot for your reply,
the link one is that which speaks about a Asynchronous clock domain crossing,
and second link is also of same kind of stuff,

But what am speaking is synchronous clock domain crossing,
i.e., there will be a relation between both the clock domain, as they will be generated from the same clock source.

for example there will a clock domain clka with 80Mhz and the other clk_b with 20Mhz,i want to know what kind of measures to be taken when the data is transferred between these clock domains.

I will be thankful if some one can help in this regard

Regards
KalyanSumankV

 

[AdvaRes]

Dear Anantha,
thanks a lot for your reply,
the link one is that which speaks about a Asynchronous clock domain crossing,
and second link is also of same kind of stuff,

But what am speaking is synchronous clock domain crossing,
i.e., there will be a relation between both the clock domain, as they will be generated from the same clock source.

for example there will a clock domain clka with 80Mhz and the other clk_b with 20Mhz,i want to know what kind of measures to be taken when the data is transferred between these clock domains.

I will be thankful if some one can help in this regard

Regards
KalyanSumankV

Hi,

I dont know if you are asking for clock synchronization or data synchronization.
For clock synchonisation even if Clk1 is a natural multiple of Clk2, if Phase Clk1-Phase CLK2 is not null then synchronization will be ensured simply by inserting 2 DFFs between the two clock domain: one DFF is drived by Clk1 that second by CLK2.

 

[kalyansumankv]

Hi,

I am actually speaking about data synchronization,
Thanks for your advice,let me try that and see if
i have any timing violations

Regards
KalyanSumankv

 

[elec-eng]

this link is for Synchronous Clock Domains Crossing

**broken link removed**

 

[raki31]

Dear Anantha,
thanks a lot for your reply,
the link one is that which speaks about a Asynchronous clock domain crossing,
and second link is also of same kind of stuff,

But what am speaking is synchronous clock domain crossing,
i.e., there will be a relation between both the clock domain, as they will be generated from the same clock source.

for example there will a clock domain clka with 80Mhz and the other clk_b with 20Mhz,i want to know what kind of measures to be taken when the data is transferred between these clock domains.

I will be thankful if some one can help in this regard

Regards
KalyanSumankV

Hi kalyan,
In synchronous clock domain crossings, as an example u took clkA with 80Mhz and clkB with 20Mhz, then take LCM of this two frequencies and calculate minimum and maximum phase shift. this phase shift will become time period for that domain crossing reg to reg path.......

In clock Tree specification file, we will group this two clocks into one Group so that clock tree algorithm balances the skew between synchronous domain crossing....
Thanku