[SOLVED] Switched Capcitor Integrator output saturation in Verilog ams

[sudeep_]

Hi All,

I used the simple Verilog ams code for simulating Switched Capcitor Integrator. I am not sure how to control the Inegrator output saturation in this code.

Can anyone help in this case to add Integrator output bounds.

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Code Verilog - [expand]
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module noninvert_integ(out, in, phi1, phi2);
input in, phi1, phi2;
voltage in;
output out;
wreal out;
wire phi1, phi2;
parameter real Cs = 1p from (0:inf);
parameter real Ci = 1p from (0:inf);
parameter real agnd = 1.65 from (0:inf);
real state, qs;
initial begin
qs = 0.0;
state = 0.0;
end
always @(negedge(phi1))
qs = Cs*(V(in)–agnd);
always @(negedge(phi2))
state = (qs + Ci*(out–agnd))/Ci;
assign out = state + agnd;
endmodule

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