Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Stupid question about FIFO & Register Definition

Status
Not open for further replies.

AdvaRes

Advanced Member level 4
Advanced Member level 4
Joined
Feb 14, 2008
Messages
1,163
Helped
113
Reputation
220
Reaction score
51
Trophy points
1,328
Location
At home
Activity points
7,442
Hi all,

I feel stupid when asking this question but I have to know that.
I know that FIFO has pointers and the shift register dont.
Can we say that Parallel in parallel out shift register is a FIFO ?
 

Hi AdvaRes,

No, you can't.

When you write data to the FIFO it will immediately available on the output.

In case of parallel in parallel out shift registers you should wait several clocks to have the data available on the output.

Bests,
Tiksan
http://syswip.com/
 

But is it a First in First out ? Why don't we classify it within the FIFO family ?
 

Indeed it is a first in first out but with a BIG latency :D
 

    AdvaRes

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top