[SOLVED] storing 4bit input to a 32 bit buffer and then output it

[electronic_jas]

Hi guys
i can give 4 bit input at a time and i have to get 32 bit output after storing them.
i was able to produce a pulse each time i gave he input and incremented the counter but when i needed to store it and give it as output using case statement the RTL is coming out correctly hence output obtained is wrong.

can ayone give me some suggestions.

here is the code after i got the output from the counter.

entity rcvval is
port (valuein,inputa:in std_logic_vector(3 downto 0);
buffertxut std_logic_vector(31 downto 0);
enableut std_logic);
end rcvval;


architecture Behavioraltwo of rcvval is
signal enablesig:std_logic:='0';
--signal buffertxsig: std_logic_vector(31 downto 0):="00000000000000000000000000000000";
signal valueinsig:std_logic_vector(3 downto 0);
begin
valueinsig<=valuein;
process(valueinsig)
--variable temp:std_logic_vector(31 downto 0):="00000000000000000000000000000000";
begin
case valueinsig is
when "0000"=>
enablesig<='0';
buffertx(31 downto 0)<="00000000000000000000000000000000";
when "0001"=>
buffertx(3 downto 0)<= inputa ;
enablesig<='0';
when "0010"=>
buffertx(7 downto 4)<= inputa ;
enablesig<='0';
when "0011"=>
buffertx(11 downto 8)<=inputa ;
enablesig<='0';
when "0100"=>
buffertx(15 downto 12)<= inputa ;
enablesig<='0';
when "0101"=>
buffertx(19 downto 16)<= inputa ;
enablesig<='0';
when "0110"=>
buffertx(23 downto 20)<= inputa ;
enablesig<='0';
when "0111"=>
buffertx(27 downto 24)<= inputa ;
enablesig<='0';
when "1000"=>
buffertx(31 downto 28)<= inputa ;
enablesig<='1';
when others=>
enablesig<='0';
--buffertxsig(31 downto 0)<=buffertxsig(31 downto 0);
end case;
enable<=enablesig;
end process;

end Behavioraltwo;