Still ESD issue -output pin protection at reversed power

[tia_design]

Still ESD issue

Very common ESD structure for an output pin is two diodes, one is connected to VDD, and the other is connected to VSS, both are reverse biased in normal operation.
For this kind of ESD structure, if output pin's voltage is within the range of VDD and VSS, the current through these two diodes are just leakage current. But in some application, if VDD and VSS are reversed, both of these two diode will be turned on and the current running through those diodes will be unlimited. To limit this current in the diodes, what kind of ESD structure has to be used?

 

[llbaobao]

Re: Still ESD issue

maybe use two back to back diode to substitute the orginal one diode can take effect?

 

[mikersia]

Still ESD issue

1) separate ESD discharge bus & N-substrate of PMOS is floating (controlled by special circuit);
2) ESD clamp to GND (GCNMOS, LVSCR, ...) & N-substrate of PMOS is floating (controlled by special circuit);
3) ...

In all cases efective (and/or distributive) Vdd/Gnd ESD clamps & back-to-back diodes between separate power domains

 

[dick_freebird]

Still ESD issue

Even if you didn't have problems at the ESD / pads, you
are still looking at a huge reverse current just from all the
now-forward-biased well junctions (and this is at one
diode, not two).

A decent ESD diode needs to conduct at least an amp
peak and is probably good for 100mA apiece continuous.
So if you have 100 pins, call it a crowbar and let the supply
deal with it, I'd say. Probably better to do your reverse
polarity protection at a higher level of assembly, since
you will probably not be the only device getting the same
abuse at the same time, so solving only your problem
is not a solution.