[SOLVED] std_logic_vector to integer conversion

[panos_papajohn]

Hi

I am trying to convert a STD_LOGIC_VECTOR to an INTEGER using the TO_INTEGER function but I get the following error :IN mode Formal SIZE of TO_SIGNED with no default value must be associated with an actual value.
Whats wrong?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity QAM_demod is
    Port ( Q_channel : in  STD_LOGIC_VECTOR (7 downto 0);
           I_channel : in  STD_LOGIC_VECTOR (7 downto 0);
           symbol : out  STD_LOGIC_VECTOR (3 downto 0);
           clk : in  STD_LOGIC);
end QAM_demod;

architecture Behavioral of QAM_demod is

signal Q : integer range -2 to 2;
signal I :integer range -2 to 2;
signal Qsigned : signed (7 downto 0);
signal Isigned : signed (7 downto 0);

signal data : std_logic_vector(3 downto 0);

begin

Qsigned <= TO_SIGNED(Q_channel);
Isigned <= TO_SIGNED(I_channel);

Q <= TO_INTEGER(Qsigned);
I <= TO_INTEGER(Isigned);

process(clk,Q,I)

begin

if (clk'event and clk ='1')
	then
			case Q is
			
				when -1  =>  
							if(I=-1)then 
							data<="0000";
							elsif(I=-2) then 
							data<="0010";
							elsif(I=1) then
							data<="1000";
							elsif(I=2) then
							data<="1010";
							else
								data<="0000";
							end if;
				when -2 =>
							if(I=-1)then 
							data<="0001";
							elsif(I=-2) then 
							data<="0011";
							elsif(I=1) then
							data<="1001";
							elsif(I=2) then
							data<="1011";
							else
								data<="0000";
							end if;
				when 1 =>
							if(I=-1)then 
							data<="0100";
							elsif(I=-2) then 
							data<="0110";
							elsif(I=1) then
							data<="1100";
							elsif(I=2) then
							data<="1110";
							else
								data<="0000";
							end if;	
				when 2 =>
							if(I=-1)then 
							data<="0101";
							elsif(I=-2) then 
							data<="0111";
							elsif(I=1) then
							data<="1101";
							elsif(I=2) then
							data<="1111";
							else
								data<="0000";
							end if;
							
				when others => data<="0000";
			end case;
			
end if; 

end process;
symbol<=data;
end Behavioral;

Thanks in advance

 

[FvM]

The error message sounds misleading, but it's clear, that the code can't compile correctly, because the integer range can't represent the signed input number without overflow. A range of -128 to 127 or an unconstraint integer would be needed to hold the result.

It may be the case, that the code gives no error with other compilers and an overflow is accepted.

P.S.: permute is right of course, the eror message isn't related to to_integer() despite of the thread title. The stated overflow problem however exists. If the problem is related to hardware design, than you should consider that an integer range of -2 to 2 is represented by signed(2 downto 0) internally. So the integer signal can take the values of -4 to 3.

In simulation, an overflow of the to_integer conversion will raise an exception.

 

[permute]

to_signed(vector, size) -- the function has two arguments, one is "size". eg
error_value <= to_signed(-1) -- how many bits is this?
x32 <= to_signed(-1, 32) -- the function returns 32b
x8 <= to_signed(-1, 8) -- 8b

 

[TrickyDicky]

The problem is that the to_signed function works on integers, not std_logic_vectors. All you need is a type conversion, not a function call:

Qsigned <= SIGNED(Q_channel);
Isigned <= SIGNED(I_channel);

Another question I have - why do you have ports of std_logic_vector when you are using signed/integer? you can used integer and signed perfectly happily on a port declaration (but stick to signed or std_logic_vector if its the top level).

 

[panos_papajohn]

Permute I did try what you said but when I used the size argument I got an error : can not have that operands in this context. In the IEEE.numeric_std library there are two TO_SIGNED functions and one of them does not use the size as argument;thats why I used it. Apparently it wasn't correct. So, can you tell me if this citation is correct (https://www.cs.umbc.edu/portal/help/VHDL/packages/numeric_std.vhd)?
FvM in a previous code I did the QAM modulator using the exact same integers and I didn't have any problems with overflows. Any ideas why?
TrickyDicky I did use the signed type on the port declaration but I wasn't sure that it was correct. This entity is connected to a IFFT which has signed outputs. So you say that it is not a problem to use it?
Really guys I appreciate your help and don't worry in a while I'll start asking more advanced questions cause am still in the learning process

Thanks

ps. If i want to have signed type ports I can't use them in a testbench file. Is there a workaround.

 

[TrickyDicky]

Why cant you use them in a testbench file? is it a generated testbench? otherwise, just modify the testbench. You should always stick with the most appropriate types, which in this case might be signed. It saves you having to do type conversions in every single file.

And FvM and Permute got it wrong in advising the to_signed function. This is not used for std_logic_vector -> signed conversion. Only integer -> signed conversion.

---------- Post added at 09:34 ---------- Previous post was at 09:31 ----------

Just to add - the numeric_std.vhd you're pointing to is an old one. There is now only 1 to_signed function.

---------- Post added at 09:35 ---------- Previous post was at 09:34 ----------

Here is the up to date one, from the VHDL website:
**broken link removed**

 

[FvM]

And FvM and Permute got it wrong in advising the to_signed function. This is not used for std_logic_vector -> signed conversion. Only integer -> signed conversion.

What do you refer to? My post was only dealing with overflow in to_integer(), in different part of the code...

FvM in a previous code I did the QAM modulator using the exact same integers and I didn't have any problems with overflows.

Q <= TO_INTEGER(Qsigned);
I <= TO_INTEGER(Isigned);

If the input value exceeds the integer range -2 to 2, Modelsim will exit the simulation with an error. If you don't observe it, you're apparently keeping the range.

In synthesized hardware, Q will overflow unnoticed.

I agree, that signed type should be used in the component interface. If it's not suitable for some reason, you can combine two type conversions in one, saving an additional signal definition.

Q <= TO_INTEGER(SIGNED(Q_channel));