Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

start discussion on verification using system verilog

Status
Not open for further replies.

mallikmarasu

Member level 3
Joined
Dec 21, 2006
Messages
58
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,288
Activity points
1,703
Guyz ,


Why cant we start a thread regarding verification using system verilog instead of multiple threads so that it is easy for anyone to follow rythem.
Here we can discuss all problems we are facing daily using sv and solutions for those.


regards
Mallik
 

For people who needs to port their legacy Vera code to SV, this is a very good script to do that. It does about 90% of the job and you need to spend a little bit of time fixing somethings yourself.

https://www.findthecat.com/vera2sv/
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top