Standard Cell Library migration to lower nodes

[pmathur]

Hi Experts,

I am kind of interested in learning/knowing Standard Cell developmental overall.

But In this thread I am more interested in learning how do they migrate a std. Cell Library to lower nodes. And what are the criteria w.r.t. to original specs for Cells like timing and power.

For example what we will let change in .lib's except our abstracts (lef) will change (obviously).

Your reply and pointers are welcome. Your reply will not only help me but perhaps build this thread a good reference point for this topic.

Thanks & Best Regards
Prashant Mathur

 

[haykp]

Hi Prashant,

I have done some queries also regarding the STD cells development flow, and haven't found the complete std development flow.

There are some books related to this subject, like Rabey book, Leblebegy and so on. However the question is still open for me also.

Thanks for opening this thread.

 

[dick_freebird]

There are tools that, once properly set up, make the porting just
a rules-deck build. The transistors are just "sticks" and a rules-
driven compaction takes a meta-library down to best-layout and
then you rerun the timing generation.

I've worked with one customer who did this for many foundries
on their in-house library, they ported it to one of our flows with
zero issues. The I/Os, however, are more of a hand-whittled job.
I forget the tool name. But it's out there (not cheap).

 

[pmathur]

Hi freebird,

Are you talking about VLM ?

 

[dick_freebird]

The tools they used were called NeoCell and NeoLinear.
I think these may have been sucked up by Cadence right
about the time of tapeout, they used to be a point tool.
Groundrule-driven layout synthesis with user modifiable
constraints (such as, I required them to use minimum two
contacts per transistor) worked pretty well, zero errors
in the compiled library & test chip. But this probably is as
much about their meta-library quality as the tool itself.