promach
Advanced Member level 4
I am trying to understand before implementing Spidergon NoC in verilog.
The original paper : Spidergon: a novel on-chip communication network
If we look at the linearized view of the spidergon NoC , we will find that spidegon NoC resembles a 2D torus with the exception on the connection mechanism of the two long wraparound wires.
1) Why mod 4 ?
2) And do you guys understand how the shortest path routing algorithm depends on the value of RelAd ?
3) Why Spidergon with 16 nodes is not deadlock-free while Spidergon with 8 nodes is deadlock-free ?
The original paper : Spidergon: a novel on-chip communication network
If we look at the linearized view of the spidergon NoC , we will find that spidegon NoC resembles a 2D torus with the exception on the connection mechanism of the two long wraparound wires.
1) Why mod 4 ?
2) And do you guys understand how the shortest path routing algorithm depends on the value of RelAd ?
3) Why Spidergon with 16 nodes is not deadlock-free while Spidergon with 8 nodes is deadlock-free ?