spartan 3E verilog code for analog to digital conversion

[Anıl Özdemirli]

Hi my name is Anil and i am working on a project that converts analog signals into digital. Referring UG230 (figure 10-4 in page 76 and figure 10-7 in page 78 ) i have written a verilog code in Xilinx ISE 8.1 . After loading the created ".bit" file into the kit, i have applied 1.5V (From the battery) to the "VINA" pin shown in figure 10-2 in page 74. My aim is to monitor 8 most significant bits on the LEDs of the kit. But i cannot see anything on the LEDs after one-time flashing. For those who have an idea about it, please help me to find my error. THANKS...

UCF FILE:

NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;

NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;

NET "L7" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "L6" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "L5" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "L4" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "L3" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "L2" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "L1" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "L0" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "sw3" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;

VERILOG CODE:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:09:39 05/11/2010
// Design Name:
// Module Name: adc_code
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module adc_code(clk,sw3,SPI_MOSI,AMP_CS,SPI_SCK,AMP_SHDN,AD_CONV,SPI_MISO,SPI_SS_B,
DAC_CS,SF_CE0,FPGA_INIT_B,L7,L6,L5,L4,L3,L2,L1,L0);

input clk,SPI_MISO,sw3;

output SPI_MOSI , AMP_CS , SPI_SCK , AMP_SHDN , AD_CONV , SPI_SS_B,
DAC_CS , SF_CE0 , FPGA_INIT_B , L7 , L6 , L5 , L4 , L3 , L2 , L1 , L0 ;

reg SPI_MOSI , AMP_CS=1'b1 , SPI_SCK=1'b0 , AMP_SHDN , AD_CONV=1'b0 , SPI_SS_B,
DAC_CS , SF_CE0 , FPGA_INIT_B , L7 , L6 , L5 , L4 , L3 , L2 , L1 , L0 ;

reg [7:0] count=8'b0;
reg [7:0] result=8'b0;


always @(posedge clk)
begin
//DISABLING OTHER SPI DEVICES
SPI_SS_B = 1'b1;
DAC_CS = 1'b1;
SF_CE0 = 1'b1;
FPGA_INIT_B = 1'b1;
AMP_SHDN = 1'b0;
//DISABLING COMPLETED

//INCREASING THE COUNTER BY "1" IN EACH 20nanoseconds.
count = count + 1'b1;

case (count[7:0])
// GAIN INITIALIZATION
0: AMP_CS=1'b1;
1: AMP_CS=1'b0;
2: AMP_CS=1'b0;
3: AMP_CS=1'b0;

// SPI_SCK BEGINS TO TOGGLE AFTER 60NANOSECONDS THAT AMP_CS BECOMES LOGIC"0"
4: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end
5: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end
6: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end
// THE DURATION OF BEING LOGIC "1" AND "0" FOR SPI_SCK IS 60NANOSECONDS.

7: SPI_SCK=1'b0;
8: SPI_SCK=1'b0;
9: SPI_SCK=1'b0;

10: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end
11: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end
12: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end

13: SPI_SCK=1'b0;
14: SPI_SCK=1'b0;
15: SPI_SCK=1'b0;

16: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end
17: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end
18: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end

19: SPI_SCK=1'b0;
20: SPI_SCK=1'b0;
21: SPI_SCK=1'b0;

22: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end
23: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end
24: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end

25: SPI_SCK=1'b0;
26: SPI_SCK=1'b0;
27: SPI_SCK=1'b0;

28: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end
29: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end
30: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end

31: SPI_SCK=1'b0;
32: SPI_SCK=1'b0;
33: SPI_SCK=1'b0;

34: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end
35: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end
36: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end

37: SPI_SCK=1'b0;
38: SPI_SCK=1'b0;
39: SPI_SCK=1'b0;

40: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end
41: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end
42: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b0; end

43: SPI_SCK=1'b0;
44: SPI_SCK=1'b0;
45: SPI_SCK=1'b0;

46: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b1; end
47: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b1; end
48: begin SPI_SCK = 1'b1 ; SPI_MOSI=1'b1; end

49: SPI_SCK=1'b0;
50: SPI_SCK=1'b0;
51: SPI_SCK=1'b0;
//DURING THE INITIALIZATION THE DATA (00000001) FOR ADJUSTING THE GAIN IS
//SENT VIA "SPI_MOSI" AT THE RISING EDGE OF "SPI_SCK"

52: AMP_CS=1'b1; // AMPLIFER DISABLED
endcase // GAIN INITIALIZATION IS OVER

if(sw3)
begin
case (count[7:0])
53: AD_CONV = 1'b1;
54: begin AD_CONV = 1'b0 ; SPI_SCK = 1'b1;end
55: SPI_SCK = 1'b1;

56: SPI_SCK = 1'b0;
57: SPI_SCK = 1'b0;

58: SPI_SCK = 1'b1;
59: SPI_SCK = 1'b1;

60: SPI_SCK = 1'b0;
61: SPI_SCK = 1'b0; // 2CYCLES OF "SPI_SCK" WITH 40NANOSECONDS PERIOD HAS PASSED

62: SPI_SCK=1'b1 ;
63: begin SPI_SCK=1'b1;result[7]=SPI_MISO;end // DATA IS CATCHED AFTER 20NANOSECODS
// THAT "SPI_SCK" HAS BECOME LOGIC"1".

64: SPI_SCK = 1'b0;
65: SPI_SCK = 1'b0;

66: SPI_SCK=1'b1 ;
67: begin SPI_SCK=1'b1;result[6]=SPI_MISO;end

68: SPI_SCK = 1'b0;
69: SPI_SCK = 1'b0;

70: SPI_SCK=1'b1 ;
71: begin SPI_SCK=1'b1;result[5]=SPI_MISO;end

72: SPI_SCK = 1'b0;
73: SPI_SCK = 1'b0;

74: SPI_SCK=1'b1 ;
75: begin SPI_SCK=1'b1;result[4]=SPI_MISO;end

76: SPI_SCK = 1'b0;
77: SPI_SCK = 1'b0;

78: SPI_SCK=1'b1 ;
79: begin SPI_SCK=1'b1;result[3]=SPI_MISO;end

80: SPI_SCK = 1'b0;
81: SPI_SCK = 1'b0;

82: SPI_SCK=1'b1 ;
83: begin SPI_SCK=1'b1;result[2]=SPI_MISO;end

84: SPI_SCK = 1'b0;
85: SPI_SCK = 1'b0;

86: SPI_SCK=1'b1 ;
87: begin SPI_SCK=1'b1;result[1]=SPI_MISO;end

88: SPI_SCK = 1'b0;
89: SPI_SCK = 1'b0;

90: SPI_SCK=1'b1 ;
91: begin SPI_SCK=1'b1;result[0]=SPI_MISO;end //ONLY 8 MSB IS CAPTURED FOR MONITORING

92: SPI_SCK = 1'b0;
93: SPI_SCK = 1'b0;

94: SPI_SCK=1'b1 ;
95: SPI_SCK=1'b1;

96: SPI_SCK = 1'b0;
97: SPI_SCK = 1'b0;

98: SPI_SCK=1'b1 ;
99: SPI_SCK=1'b1;

100: SPI_SCK = 1'b0;
101: SPI_SCK = 1'b0;

102: SPI_SCK=1'b1 ;
103: SPI_SCK=1'b1;

104: SPI_SCK = 1'b0;
105: SPI_SCK = 1'b0;

106: SPI_SCK=1'b1 ;
107: SPI_SCK=1'b1;

108: SPI_SCK = 1'b0;
109: SPI_SCK = 1'b0;

110: SPI_SCK=1'b1 ;
111: SPI_SCK=1'b1;

112: SPI_SCK = 1'b0;
113: SPI_SCK = 1'b0;

114: SPI_SCK=1'b1 ;
115: SPI_SCK=1'b1;

116: SPI_SCK = 1'b0;
117: SPI_SCK = 1'b0;

// 2 BLANK CYCLE + 14 FOR DATA + 2 FOR FINISHING
// = 18 "SPI_SCK" CYCLE BEGINS FROM CASE "118"

118: begin SPI_SCK = 1'b1 ; {L7,L6,L5,L4,L3,L2,L1,L0}=result[7:0]; end
119: SPI_SCK = 1'b1; // RESULT IS MONITORED AT THE LEDS AT CASE "118"

120: SPI_SCK = 1'b0;
121: SPI_SCK = 1'b0;

122: SPI_SCK = 1'b1;
123: SPI_SCK = 1'b1;

124: SPI_SCK = 1'b0;
125: SPI_SCK = 1'b0;

126: SPI_SCK = 1'b1;
127: SPI_SCK = 1'b1;

128: SPI_SCK = 1'b0;
129: SPI_SCK = 1'b0;

130: SPI_SCK = 1'b1;
131: SPI_SCK = 1'b1;

132: SPI_SCK = 1'b0;
133: SPI_SCK = 1'b0;

134: SPI_SCK = 1'b1;
135: SPI_SCK = 1'b1;

136: SPI_SCK = 1'b0;
137: SPI_SCK = 1'b0;

138: SPI_SCK = 1'b1;
139: SPI_SCK = 1'b1;

140: SPI_SCK = 1'b0;
141: SPI_SCK = 1'b0;

142: SPI_SCK = 1'b1;
143: SPI_SCK = 1'b1;

144: SPI_SCK = 1'b0;
145: SPI_SCK = 1'b0;

146: SPI_SCK = 1'b1;
147: SPI_SCK = 1'b1;

148: SPI_SCK = 1'b0;
149: SPI_SCK = 1'b0;

150: SPI_SCK = 1'b1;
151: SPI_SCK = 1'b1;

152: SPI_SCK = 1'b0;
153: SPI_SCK = 1'b0;

154: SPI_SCK = 1'b1;
155: SPI_SCK = 1'b1;

156: SPI_SCK = 1'b0;
157: SPI_SCK = 1'b0;

158: SPI_SCK = 1'b1;
159: SPI_SCK = 1'b1;

160: SPI_SCK = 1'b0;
161: SPI_SCK = 1'b0;

162: SPI_SCK = 1'b1;
163: SPI_SCK = 1'b1;

164: SPI_SCK = 1'b0;
165: SPI_SCK = 1'b0;

166: SPI_SCK = 1'b1;
167: SPI_SCK = 1'b1;

168: SPI_SCK = 1'b0;
169: SPI_SCK = 1'b0;

170: SPI_SCK = 1'b1;
171: SPI_SCK = 1'b1;

172: SPI_SCK = 1'b0;
173: SPI_SCK = 1'b0;

174: SPI_SCK = 1'b1;
175: SPI_SCK = 1'b1;

176: SPI_SCK = 1'b0;
177: SPI_SCK = 1'b0;

178: SPI_SCK = 1'b1;
179: SPI_SCK = 1'b1;

180: SPI_SCK = 1'b0;
181: SPI_SCK = 1'b0;

182: SPI_SCK = 1'b1;
183: SPI_SCK = 1'b1;

184: SPI_SCK = 1'b0;
185: SPI_SCK = 1'b0;

186: SPI_SCK = 1'b1;
187: SPI_SCK = 1'b1;

188: begin SPI_SCK = 1'b0 ; result[7:0]=8'b0;end // RESULT IS ERASED
189: SPI_SCK = 1'b0 ;

default: count[7:0]=8'b00000000; // RETURNING TO CASE "53"
endcase
end
end
endmodule

 

[vipinlal]

Is your code working properly in simulation?
Make sure that the LED's doesnt turn ON and OFF very fast.Then it is difficult to see the change in them.If its so fast then I suggest you to scale down the clock frequency by considerable amount.The LED's should change by maximum of 5 times per second.Adjust your clock frequency like that.

--vipin
https://vhdlguru.blogspot.com/

 

[Anıl Özdemirli]

I do not know how to simulate the code. But there is no syntax error.Also I have forgotten to imply that. I have scaled down the clock frequency down to 1 Hz and nothing has changed. Also, maximum change in a LED (10ns) can be seen as a weak light on the LED. But my LEDs are never giving light.

 

[umer_366]

ok i am providing u my code plz check it out...
its sparten 3E ADC ISE code

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:47:48 05/15/2010
// Design Name:
// Module Name: spi_master_adc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: we have designed a state machine to implement this control interface for ADC.
// there are 3 states;
// 1) idle state : This is the initial state in which we trigger the AD_CONV signal to start the conversion process.
// 2) convert state : this is the main state in which we convert and load our digitally converted data into a temporary register.
// 3) read state : in this state we read the final digital output
//
//////////////////////////////////////////////////////////////////////////////////
module spi_master_adc(

input SPI_MISO,
input CLKIN,

output reg AD_CONV,
output SPI_SCK,
output reg [27:0] ADC_DIGITAL,
output reg READY
);

parameter idle = 3'b001;
parameter convert = 3'b010;
parameter read = 3'b100;


reg [2:0] state= idle;
reg idle_count = 0;
reg [5:0] count=0;
reg [27:0] data;

initial
AD_CONV = 1;




// the clken signal control the clock signal sent to the adc.
// we want SPI_SCK for 33 clock cycles so we enable clken for only that duration of time.
assign SPI_SCK = CLKIN;

always@(posedge CLKIN)
begin

case(state)
idle : begin

// ready signal si set to zero to indicate output is not ready.
READY <= 0;
if(idle_count == 0) begin
// conversion is disabled
AD_CONV <= 1;
state <= idle;
idle_count <= idle_count + 1;
end
else begin
// reset the counting variable and goes to conversion state after 1 clock cycle
idle_count <= 0;
state <= convert;

end
end

convert: begin

READY <= 0;
// start the conversion process and enable the output clock.
AD_CONV <= 0;
if(count != 33)begin

// read the data only when the input isnot in high impedance state
if((count != 0) | (count != 1) | (count != 17) | (count != 33) ) begin
data <= data << 1;
data[0] <= SPI_MISO;
end

// updates the counter

end
else
begin
// after 33 cycles .. goes to read state
state <= read;
count <= 0;
end
count <= count + 1;
end
read : begin
// stops the output clock . stops the conversion and outputs the digital data.
count <= 0;
AD_CONV <= 0;
ADC_DIGITAL <= data;
READY <= 1;
// goesto idle state to start new conversion process.
state <= idle;
end
endcase

end

endmodule


and 2nd is



`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:35:44 05/15/2010
// Design Name:
// Module Name: spi_master_amp
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi_master_amp(

input CLKIN, // CLOCK SOURCE FROM DCM (DIGITAL CLOCK MANAGER)
input RST,
input [7:0] GAIN_AB, // GAIN OF AMPLIFIER A AND B FROM MICROBLAZE
input ADC_DOUT, // PREVIOUS GAIN SERIAL INPUT FROM AMPIFIER
input WREN, // WRITE ENABLE FOR GAIN FROM MICROBLAZE
output reg AMP_CS, //CONTROL SIGNAL TO AMPLIFIER
output SPI_SCK, // CLOCK SIGNAL TO AMPLIFIER (10MHZ)
output reg SPI_MOSI, //SERIAL INPUT TO AMPLIFIER
output reg AMP_SHDN // RESET SIGNAL FOR AMPIFIER


);

reg [7:0] gain;
reg [3:0] count;
reg done = 0;

assign SPI_SCK = CLKIN;

always@(posedge CLKIN)
begin
if(RST)
AMP_SHDN <= 1;
else
begin
AMP_SHDN <= 0;

if(WREN) begin
gain <= GAIN_AB;
done <= 0;
end
else begin

{SPI_MOSI,gain} <= gain << 1;

if(count == 8) begin
done <= 1;
count <= 0;
end
else
count <= count + 1;


end
end

end

always@(negedge CLKIN)
begin

if(WREN | done)
AMP_CS <= 1;
else
AMP_CS <= 0;


end

endmodule




then combine bothe of these modules i schematic and then apply them through XPS......

 

[princez]

hay every one, i am new to verilog, tried to make some small programs like clock etc. now i want to design an ADC chip as one of my course projects. actually i want to design a chip that works as and ADC if the mode pin is high and DAC if its low. plz gude me out, and suggest me that if its a nice project or not? and will a person having little verilog knowledge be able to do this?

i would really appriciate if u provide me with some links and reading stuff..

thx and regards..

 

[deepanwita@gmail.com]

can you tell me the procedure to check the out put of the adc in led or through ChipScope Pro 11.1 Software after burn the program in spartan 3e kit board................and give the vhdl code of the spartan 3e adc interfacing ...................plz help me... its urgent.......................plzzzzzzzzzz

 

[deepanwita@gmail.com]

ok i am providing u my code plz check it out...
its sparten 3E ADC ISE code

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:47:48 05/15/2010
// Design Name:
// Module Name: spi_master_adc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: we have designed a state machine to implement this control interface for ADC.
// there are 3 states;
// 1) idle state : This is the initial state in which we trigger the AD_CONV signal to start the conversion process.
// 2) convert state : this is the main state in which we convert and load our digitally converted data into a temporary register.
// 3) read state : in this state we read the final digital output
//
//////////////////////////////////////////////////////////////////////////////////
module spi_master_adc(

input SPI_MISO,
input CLKIN,

output reg AD_CONV,
output SPI_SCK,
output reg [27:0] ADC_DIGITAL,
output reg READY
);

parameter idle = 3'b001;
parameter convert = 3'b010;
parameter read = 3'b100;


reg [2:0] state= idle;
reg idle_count = 0;
reg [5:0] count=0;
reg [27:0] data;

initial
AD_CONV = 1;




// the clken signal control the clock signal sent to the adc.
// we want SPI_SCK for 33 clock cycles so we enable clken for only that duration of time.
assign SPI_SCK = CLKIN;

always@(posedge CLKIN)
begin

case(state)
idle : begin

// ready signal si set to zero to indicate output is not ready.
READY <= 0;
if(idle_count == 0) begin
// conversion is disabled
AD_CONV <= 1;
state <= idle;
idle_count <= idle_count + 1;
end
else begin
// reset the counting variable and goes to conversion state after 1 clock cycle
idle_count <= 0;
state <= convert;

end
end

convert: begin

READY <= 0;
// start the conversion process and enable the output clock.
AD_CONV <= 0;
if(count != 33)begin

// read the data only when the input isnot in high impedance state
if((count != 0) | (count != 1) | (count != 17) | (count != 33) ) begin
data <= data << 1;
data[0] <= SPI_MISO;
end

// updates the counter

end
else
begin
// after 33 cycles .. goes to read state
state <= read;
count <= 0;
end
count <= count + 1;
end
read : begin
// stops the output clock . stops the conversion and outputs the digital data.
count <= 0;
AD_CONV <= 0;
ADC_DIGITAL <= data;
READY <= 1;
// goesto idle state to start new conversion process.
state <= idle;
end
endcase

end

endmodule


and 2nd is



`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:35:44 05/15/2010
// Design Name:
// Module Name: spi_master_amp
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi_master_amp(

input CLKIN, // CLOCK SOURCE FROM DCM (DIGITAL CLOCK MANAGER)
input RST,
input [7:0] GAIN_AB, // GAIN OF AMPLIFIER A AND B FROM MICROBLAZE
input ADC_DOUT, // PREVIOUS GAIN SERIAL INPUT FROM AMPIFIER
input WREN, // WRITE ENABLE FOR GAIN FROM MICROBLAZE
output reg AMP_CS, //CONTROL SIGNAL TO AMPLIFIER
output SPI_SCK, // CLOCK SIGNAL TO AMPLIFIER (10MHZ)
output reg SPI_MOSI, //SERIAL INPUT TO AMPLIFIER
output reg AMP_SHDN // RESET SIGNAL FOR AMPIFIER


);

reg [7:0] gain;
reg [3:0] count;
reg done = 0;

assign SPI_SCK = CLKIN;

always@(posedge CLKIN)
begin
if(RST)
AMP_SHDN <= 1;
else
begin
AMP_SHDN <= 0;

if(WREN) begin
gain <= GAIN_AB;
done <= 0;
end
else begin

{SPI_MOSI,gain} <= gain << 1;

if(count == 8) begin
done <= 1;
count <= 0;
end
else
count <= count + 1;


end
end

end

always@(negedge CLKIN)
begin

if(WREN | done)
AMP_CS <= 1;
else
AMP_CS <= 0;


end

endmodule




then combine bothe of these modules i schematic and then apply them through XPS......

sir,
r u complete adc interface in spartan 3e?? if u complete the adc can you help me to do the interfacing of adc in spartan 3e??
can you tell me the procedure to check the out put of the adc in led or through ChipScope Pro 11.1 Software after burn the program in spartan 3e kit board................and give the vhdl or verilog code of the spartan 3e adc interfacing ...................plz help me... its urgent.......................plzzzzzzzzzz
i attached my ise project below.pls check it.....pls help me its urgent .....................