hodahussein
Full Member level 2
dear all
i am using ise 12.1 (ip core-> memory interfacing generator) i read about this tools and i know that it is {tool generates DDR SDRAM interfaces Spartan-3E. The tool takes inputs such as the memory interface type, FPGA family, FPGA devices, frequencies, data width, memory mode register values, and so forth, from the user through a graphical user interface (GUI). The tool generates RTL, SDC, UCF, and document files as output}
and through user guid for MIG i observed that :MIG Output of the DDR SDRAM Controller Design with a DCM and a Testbench what does it mean?
when i generate DDR SDRAM interface for spartan 3E fpga for first trial i see that the component declaration in .vho file contains that
--------------------------------------------
component mig_v3_4
port(
cntrl0_ddr_dq : inout std_logic_vector(7 downto 0);
cntrl0_ddr_a : out std_logic_vector(12 downto 0);
cntrl0_ddr_ba : out std_logic_vector(1 downto 0);
cntrl0_ddr_cke : out std_logic;
cntrl0_ddr_cs_n : out std_logic;
cntrl0_ddr_ras_n : out std_logic;
cntrl0_ddr_cas_n : out std_logic;
cntrl0_ddr_we_n : out std_logic;
cntrl0_ddr_dm : out std_logic_vector(0 downto 0);
cntrl0_rst_dqs_div_in : in std_logic;
cntrl0_rst_dqs_div_out : out std_logic;
sys_clkb : in std_logic;
sys_clk : in std_logic;
reset_in_n : in std_logic;
cntrl0_burst_done : in std_logic;
cntrl0_init_val : out std_logic;
cntrl0_ar_done : out std_logic;
cntrl0_user_data_valid : out std_logic;
cntrl0_auto_ref_req : out std_logic;
cntrl0_user_cmd_ack : out std_logic;
cntrl0_user_command_register : in std_logic_vector(2 downto 0);
cntrl0_clk_tb : out std_logic;
cntrl0_clk90_tb : out std_logic;
cntrl0_sys_rst_tb : out std_logic;
cntrl0_sys_rst90_tb : out std_logic;
cntrl0_sys_rst180_tb : out std_logic;
cntrl0_user_data_mask : in std_logic_vector(1 downto 0);
cntrl0_user_output_data : out std_logic_vector(15 downto 0);
cntrl0_user_input_data : in std_logic_vector(15 downto 0);
cntrl0_user_input_address : in std_logic_vector(24 downto 0);
cntrl0_ddr_dqs : inout std_logic_vector(0 downto 0);
cntrl0_ddr_ck : out std_logic_vector(0 downto 0);
cntrl0_ddr_ck_n : out std_logic_vector(0 downto 0)
);
--------------------------------------------
but when i check th user manual for spartan 3E kit i found that
address [12 to 0]
data [15 to 0]
control signal = 14 pin
why the generator create the other ports? i can not understand
-how i can use the out file in my vhdl code?
- can any one tell about MIG more infromation and any code reference to me
wait your help
i am using ise 12.1 (ip core-> memory interfacing generator) i read about this tools and i know that it is {tool generates DDR SDRAM interfaces Spartan-3E. The tool takes inputs such as the memory interface type, FPGA family, FPGA devices, frequencies, data width, memory mode register values, and so forth, from the user through a graphical user interface (GUI). The tool generates RTL, SDC, UCF, and document files as output}
and through user guid for MIG i observed that :MIG Output of the DDR SDRAM Controller Design with a DCM and a Testbench what does it mean?
when i generate DDR SDRAM interface for spartan 3E fpga for first trial i see that the component declaration in .vho file contains that
--------------------------------------------
component mig_v3_4
port(
cntrl0_ddr_dq : inout std_logic_vector(7 downto 0);
cntrl0_ddr_a : out std_logic_vector(12 downto 0);
cntrl0_ddr_ba : out std_logic_vector(1 downto 0);
cntrl0_ddr_cke : out std_logic;
cntrl0_ddr_cs_n : out std_logic;
cntrl0_ddr_ras_n : out std_logic;
cntrl0_ddr_cas_n : out std_logic;
cntrl0_ddr_we_n : out std_logic;
cntrl0_ddr_dm : out std_logic_vector(0 downto 0);
cntrl0_rst_dqs_div_in : in std_logic;
cntrl0_rst_dqs_div_out : out std_logic;
sys_clkb : in std_logic;
sys_clk : in std_logic;
reset_in_n : in std_logic;
cntrl0_burst_done : in std_logic;
cntrl0_init_val : out std_logic;
cntrl0_ar_done : out std_logic;
cntrl0_user_data_valid : out std_logic;
cntrl0_auto_ref_req : out std_logic;
cntrl0_user_cmd_ack : out std_logic;
cntrl0_user_command_register : in std_logic_vector(2 downto 0);
cntrl0_clk_tb : out std_logic;
cntrl0_clk90_tb : out std_logic;
cntrl0_sys_rst_tb : out std_logic;
cntrl0_sys_rst90_tb : out std_logic;
cntrl0_sys_rst180_tb : out std_logic;
cntrl0_user_data_mask : in std_logic_vector(1 downto 0);
cntrl0_user_output_data : out std_logic_vector(15 downto 0);
cntrl0_user_input_data : in std_logic_vector(15 downto 0);
cntrl0_user_input_address : in std_logic_vector(24 downto 0);
cntrl0_ddr_dqs : inout std_logic_vector(0 downto 0);
cntrl0_ddr_ck : out std_logic_vector(0 downto 0);
cntrl0_ddr_ck_n : out std_logic_vector(0 downto 0)
);
--------------------------------------------
but when i check th user manual for spartan 3E kit i found that
address [12 to 0]
data [15 to 0]
control signal = 14 pin
why the generator create the other ports? i can not understand
-how i can use the out file in my vhdl code?
- can any one tell about MIG more infromation and any code reference to me
wait your help