ptjw
Junior Member level 3
hello all,
i mentioned a few weeks ago that i am doing a project which uses a Spartan 3A FPGA to read info from an SD card. this info tells the FPGA to route certain input signals to the output signals like if i want the signal from input 1 to be repeated at output 1 or 3 i can just change the data on the SD card and it will be done. (so much easier said than done..)
anyway i've run into a brick wall during the last phase of my code: during the assigning of output ports.
basically Xilinx ISE tells me that i have used up more than 100% of the device's resources...i have edited my code and by elimination, i have found the problem. my main code is really long and in a mess now but this is the primary culprit:
the arrayed variables on the left are the output ports while the variables on the right are the input ports. the variables with the '_BUF' are integers with a range of 1 to 40. when synthesizing this code i get this:
as you can see, this is totally not cool because this means my code can't be implemented into hardware (i'm guessing due to acute inefficiency from my inexperience in VHDL
)
anyway, if i assign a random integer into the output port arrays, i use much lesser resources:
it's a drastic difference in amount of resources used, but i need to put the _BUF variables there because they hold the data retrieved from the SD card for routing the inputs to outputs. am i missing something here? i hope i'm doing something wrong and that there's a more efficient way of doing this...
i declared the _BUF variables like so:
i mentioned a few weeks ago that i am doing a project which uses a Spartan 3A FPGA to read info from an SD card. this info tells the FPGA to route certain input signals to the output signals like if i want the signal from input 1 to be repeated at output 1 or 3 i can just change the data on the SD card and it will be done. (so much easier said than done..)
anyway i've run into a brick wall during the last phase of my code: during the assigning of output ports.
basically Xilinx ISE tells me that i have used up more than 100% of the device's resources...i have edited my code and by elimination, i have found the problem. my main code is really long and in a mess now but this is the primary culprit:
Code:
FPGA_OUT(CLKLCD_BUF) <= CLKLCD;
FPGA_OUT(LCD_RESET_BUF) <= LCD_RESET;
FPGA_OUT(CS1_BUF) <= CS1;
FPGA_OUT(CS2_BUF) <= CS2;
FPGA_OUT(A0_BUF) <= A0;
FPGA_OUT(WR_BUF) <= WR;
FPGA_OUT(RD_SDA_BUF) <= RD_SDA;
FPGA_OUT(CLKIN_BUF) <= CLKIN;
FPGA_OUT(D0_BUF) <= D0;
FPGA_OUT(D1_BUF) <= D1;
FPGA_OUT(D2_BUF) <= D2;
FPGA_OUT(D3_BUF) <= D3;the arrayed variables on the left are the output ports while the variables on the right are the input ports. the variables with the '_BUF' are integers with a range of 1 to 40. when synthesizing this code i get this:
Code:
Selected Device : 3s50atq144-4
Number of Slices: 894 out of 704 126% (*)
Number of Slice Flip Flops: 242 out of 1408 17%
Number of 4 input LUTs: 1613 out of 1408 114% (*)
Number of IOs: 67
Number of bonded IOBs: 63 out of 108 58%
Number of GCLKs: 1 out of 24 4%
WARNING:Xst:1336 - (*) More than 100% of Device resources are usedas you can see, this is totally not cool because this means my code can't be implemented into hardware (i'm guessing due to acute inefficiency from my inexperience in VHDL
) anyway, if i assign a random integer into the output port arrays, i use much lesser resources:
Code:
FPGA_OUT(1) <= CLKLCD;
FPGA_OUT(2) <= LCD_RESET;
FPGA_OUT(3) <= CS1;
FPGA_OUT(4) <= CS2;
FPGA_OUT(5) <= A0;
FPGA_OUT(6) <= WR;
FPGA_OUT(7) <= RD_SDA;
FPGA_OUT(8) <= CLKIN;
FPGA_OUT(9) <= D0;
FPGA_OUT(10) <= D1;
FPGA_OUT(11) <= D2;
FPGA_OUT(12) <= D3;
Code:
Selected Device : 3s50atq144-4
Number of Slices: 122 out of 704 17%
Number of Slice Flip Flops: 105 out of 1408 7%
Number of 4 input LUTs: 236 out of 1408 16%
Number of IOs: 67
Number of bonded IOBs: 35 out of 108 32%
Number of GCLKs: 1 out of 24 4%it's a drastic difference in amount of resources used, but i need to put the _BUF variables there because they hold the data retrieved from the SD card for routing the inputs to outputs. am i missing something here? i hope i'm doing something wrong and that there's a more efficient way of doing this...
i declared the _BUF variables like so:
Code:
variable CLKLCD_BUF : integer range 0 to 40 := 0;
variable LCD_RESET_BUF : integer range 0 to 40 := 0;
variable CS1_BUF : integer range 0 to 40 := 0;
variable CS2_BUF : integer range 0 to 40 := 0;
variable A0_BUF : integer range 0 to 40 := 0;
variable WR_BUF : integer range 0 to 40 := 0;
variable RD_SDA_BUF : integer range 0 to 40 := 0;
variable CLKIN_BUF : integer range 0 to 40 := 0;
variable D0_BUF : integer range 0 to 40 := 0;
variable D1_BUF : integer range 0 to 40 := 0;
variable D2_BUF : integer range 0 to 40 := 0;
variable D3_BUF : integer range 0 to 40 := 0;
variable D4_BUF : integer range 0 to 40 := 0;
variable D5_BUF : integer range 0 to 40 := 0;
variable D6_BUF : integer range 0 to 40 := 0;
variable D7_BUF : integer range 0 to 40 := 0;
