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There are many factors.
1. Fabrication capability
Smaller spacing will be more expensive to manufacture, and each PCB manufacturer has some limits of their own.
2. Soldering
You will also have to consider your capability of soldering fine pattern PCB.
3. Safety
If the voltage between traces is high, you have to maintain certain clearance.
If the board has to be certified by UL, CSA or similar safety agencies, you need to check with each standard.
If it is just for your experiment in the lab, 0.13mm spacing is okay upto 100Vdc or ac peak. 0.76mm for 300 to 500V.
If it is internal layers of multilayer board, you can use smaller gap.
Hope this helps.
S. H.
According to above reply it seems that only the voltage level of the trace and cost is the major factor for deciding the airgap between trace.
What about the frequency of the signal will this not come into picture?Will trace width of the signal not is the other deciding factor.
Where i can get the actual information about the airgap b/w the traces,what about interface type like LVDS and PCI each having some fixed air gap b/w.
Of course, trace clearance and width are influencing impedance respectively capacitance and inductance per length unit. Furthermore, crosstalk signal integrity rules can require increased clearance for some nets.
For digital designs without additional requirements, you usually set design rules for standard net class to minimum width and clearance available in the targetted PCB technology, e. g. 150 µm (6 mils) as an today's industry standard supported by all manufaturers without extra costs. With plenty of board space, it may be increased to 200 µm (8 mils).
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