SOS! Some Problems on the Design of PLL!

[dopradar]

Hi all.

Recently I am designing a 2.5GHz PLL.and met some problems.

1.The select of reference crystal. Which one should be selected,sine wave or square wave? :?:

2.For the PD charge pump output,it should be pulses. But whether it is correct that the pulses after passing loop-filter still be pulses? :?:


Thank you for your help!

 

[radiohead]

1. You don't care about the waveform of the reference clock. Only the phase noise counts.
2. The loop filter filters out the spikes and at the input of the VCO the only thing that remains is a DC voltage and some noise. The very small unsupressed spike rememnants cause spurs.

 

[dopradar]

Thank you,radiohead!

I have another preblem:
I use the AnalogDevices ADF4113 as PD.
I test the N Divider Output is pulses,the R Divider Output is also pulses,but the CP Ouput(ChargePumpOutput)is not pulses.
I am puzzle!

 

[toonafishy]

If the synthesizer is out of lock, then the PD will put out only 0 volts or VCC volts. When the phase of the RF and the reference are within 2 pi radians, the voltage will then turn into pulses. When the PLL is locked, the pulses will become very narrow and may be hard to see. However at this point, the narrow pulses are integrated by the loop filter and produce the VCO contol voltage needed to lock the VCO, This final voltge should be somewhere between 0 and VCC volts.

 

[radiohead]

Check your PLL registers: are the dividers ok? You can check that by using the muxout pin as an output.

The next thing is: is your PD polarity okay? If this is not the case your system can impossibly lock.

Finally, check if you have instabilities of your loop opamp. They result in queer things.

 

[Japp]

So is the output not pulsed, but the PLL is in lock ?(and the tuning voltage is between gnd and vcc) if so I guess you don´t have a problem but if it is still not in a locked condition try some of the following;
Check the frequency out of the Reference divider and the Prescaler (as stated above..) are they comparable (and is it the expected VCO freq divided by N)?
If the Prescaler frequency is lower than the reference frequency the VCO frequency is to low and the loop should increase the vco frequency (so the tune-voltage should be high, or viceverse if the Prescaler frequency is higher than the ref.freq.). If the tune voltage is 0 volt the PD polarity must be wrong. If the tune voltage is at maximum (VCC?) and the frequency is still to low the VCO does not cover the expected range!. This could e.g. happen with a band-switched vco where the band-setting is wrong.