Some concern of integrate rectify diode in DC-DC layout

[iceplanet]

Now i have a design of 5V input buck DC-DC, it demand integrate rectify diode in the chip, it will use 0.5um double-well CMOS process. In order to minimize the layout, i would like to use the parasitic n+/pwell diode of nmos(power switch) as the rectify diode, but i'm worried that it will cause latch-up problem because of the injectin of current into p-sub! So, if it is feasible to use parasitic n+/pwell diode, what should i take into considration in the layout.
Thanks for advice!

 

[erikl]

... what should i take into considration in the layout.

Here is an advice for a 0.18µm double-well CMOS process: Use 2 guard rings: View attachment Prevent_latch-up.pdf
Connect the p+/p-well guard ring to GND, the n+/n-well guard ring to VDD.

 

[iceplanet]

Here is an advice for a 0.18µm double-well CMOS process: Use 2 guard rings: View attachment 50055
Connect the p+/p-well guard ring to GND, the n+/n-well guard ring to VDD.

Thanks for advice
So you think it's feasible to forward bias parasitic n+/pwell diode if i take the advice you provide, right?

 

[mikersia]

From my viewpoint it is better to avoide to use a forward biased N+/Pwell diode, if current throug them will not limited to a small values. The more current will flow through such diode, the more surrounding collectors would be involved, not only nearest guard ring. If nearby will be a sensitive block, then it's operation can be influenced,- up to switching-off.

 

[erikl]

So you think it's feasible to forward bias parasitic n+/pwell diode if i take the advice you provide, right?

In principle, yes; I've used such diodes (several in series) for gate voltage limitation at high-side HV LDPMOS transistors. The current density, however, was only in the order of 100nA/(µm)² for a Vf=0.7V , i.e. you'd need a huge die area of 100×100 µm² for a forward current of only 1mA (for the a.m. forward voltage) - apart from the guard rings' area consumption.

BTW: I wouldn't call it parasitic, if its usage is intended ;-)

 

[dick_freebird]

Why not use synchronous rectification like just about
everybody else? Using a PN diode as the freewheel
sets your max efficiency pretty low when you are
making low voltage outputs.

 

[iceplanet]

Why not use synchronous rectification like just about
everybody else? Using a PN diode as the freewheel
sets your max efficiency pretty low when you are
making low voltage outputs.

Thanks for you advice
I would like to use synchronous rectification as you say, but there is dead region when diode should conduct current.

---------- Post added at 12:44 ---------- Previous post was at 12:20 ----------

From my viewpoint it is better to avoide to use a forward biased N+/Pwell diode, if current throug them will not limited to a small values. The more current will flow through such diode, the more surrounding collectors would be involved, not only nearest guard ring. If nearby will be a sensitive block, then it's operation can be influenced,- up to switching-off.

What you say is what i worry about, the current though the diode not only increase the probability of latch-up, but also intervene the sensitive block nearby. But it is the demand of my design to intergrate diode into the circuit, so what i concern is to minimize the adverse infuence of it. I has even thinked about to add n-buried layer to collect carrier, but this way will increase the expense of manufacture, and i don't know how much benefit this n-buried layer will bring on...

---------- Post added at 13:05 ---------- Previous post was at 12:44 ----------

In principle, yes; I've used such diodes (several in series) for gate voltage limitation at high-side HV LDPMOS transistors. The current density, however, was only in the order of 100nA/(µm)² for a Vf=0.7V , i.e. you'd need a huge die area of 100×100 µm² for a forward current of only 1mA (for the a.m. forward voltage) - apart from the guard rings' area consumption.

BTW: I wouldn't call it parasitic, if its usage is intended ;-)

You experience encourges me I was intended to use BCD process to implement my design at the first time, but because of the high price of this process, i turn to CMOS process which i think is adequate to fulfill my design. but i think the LDMOS has advantage compared to CMOS at this point because its parasitic body diode has isolated from substrate.

 

[dick_freebird]

There's "isolated" and there's isolated.

Your pin ESD clamp might be the backstop freewheel
diode. At least this has probably been characterized
out to some reasonable peak (if not quasi-DC) current
and you could get that info, and increase size to suit.

Still you would prefer that an "on" MOSFET carry the
current except for the dead (nonoverlap) time.

 

[erikl]

Re: LDMOS advantage

... i think the LDMOS has advantage compared to CMOS at this point because its parasitic body diode has isolated from substrate.

Yes. Moreover, its body can be connected to the highest potential, respectively, if 4- (or effectively 5- ) -terminal LDPMOS is provided (and well modeled ;-) ).