SOC Encounter question

[kolla]

insert black box in soc encounter

Hi friends,

Can someone tell me whether Cadence SOC Encounter can be used to
build SOCs with FPGA Hard Macros (IP)? If not what tool can do that?

Thanks in advance

 

[kumar_eee]

connecting a block in encounter

I dont think you can use FPGA Hard Macros in SOC Back-end. The FPGA architecture(CLB) is totally different from SOC architecture.

when you do Logic synthesis, you need to provide the FPGA model. You wil try to get the netlist according to your FPGA model architecture.

There are many points to note.
1. Timing Numbers
2. DFT requirements
3. Physical Design rules ( DRC/LVS)
4. DFM requirements
5. Power requirements

I'm not sure about the tools.

Others can share their views.

 

[kolla]

fpga encounter

Thanks kumar. So is it correct to say that all my Hard Macros that I'm
bringing into SOC encounter must be ASIC blocks made for a specific
process technology and they come in as gds/lef?

 

[cop02ia]

Hi,
I'm not sure how you want to interface the FPGA but consider it this way, from the manufacturers point of view, a chip has to be created layer-by-layer, thus mixing between technology process (e.g. 45nm & 250nm) would be almost impossible since the wafer has to be transferred out of the clean room when creating for 1 process then transferring to another clean room.
Now considering that the FPGA is already a completed device with I/O connections and all, so shouldn't connection between a chip & the FPGA device be on PCB?

To create FPGAs, you can checkout Altera or Xilinx website for the required tools. FPGAs are already physically created. Hence, they don't need physical manufacturing considerations such as DRC/LVS checks, etc. 'Place & Route' in FPGA means that according to your RTL code, the tool will look at which devices & connections to use (which are already built in the FPGA chip), instead of having to build them from scratch like ASIC. The devices which aren't used are redundant & not used (which means some space is wasted).

Maybe someone can give a better explanation. Anyway, hope this much helps.

 

[kolla]

Thanks cop02ia !! That was indeed very informative as I'm still learning
these things. This makes sense now.. and I see why we can't use FPGAs
on an ASIC SOC.

I saw somewhere that a Hard Macro is defined as "a block generated in a
methodology other than P&R". This confuses me a bit...can you help explain
this further? I thought a Hard IP is a block which went thru P&R for
some technology process and delivered to the end customer as GDS/LEF
so that the customer can instantiate that in their gate-level netlist as a black
box. Then the customer would run a tool like SOCE to P&R that netlist and
use the IP LEF properties (pins & shape info) for hooking up that within the
design.

 

[cop02ia]

Hi,
I believe you're right.
If a block is created other than P&R (or custom drawn such as for mixed-signal), I can't see any way of implementing the hard macro.
If you look at the hard macro LEFs, there should be pin & metal blockages which suggests that they are using ASIC.
To connect to this block, your signals would just have to hook up to the pins.

Furthermore, some blocks allow you to do routing over them, for example a DLL IP block might use up to 4 metal layers, while your design (which will be using the same process technology) may utilize up to 6 metal layers.
Hence, you might want to route signals using metal 5 or 6 over the block. Of course, routing will be long & SI issues have to be taken into consideration.

 

[kolla]

Thanks cop02ia ! very helpful answer again.
Are you familiar with SOC Encounter? Does it allow building an SOC with
both Analog & Digital hard macros? If so how does SOCE helps marry
these A & D blocks into an SOC? (any specific features or methods in SOCE)
These are some of the answers I'm looking for ...

 

[cop02ia]

Hi,
Cadence has a flow called AMS (Analog-Mixed Signal if I'm not mistaken). Here, you can work on the Analog part with Verilog-A codes to describe the digital signal inputs going into the analog world.
Setting up for simulation wasn't as straight forward as normal analog simulations so I foorgot most of the procedures. I've never really used it but have learned it briefly though.

I've worked on the digital part of a mixed design before (not in detail though, and not a critical device) in SOC & the analog part was confined to hard macros (like any other digital hard macro) so all I saw was black-boxes with pins which had to connect to the digital signals.

The digital floorplan was not rectangular because of the analog I/O parts, which meant that routing could be tight in some places, but the flow was generally the same: just treat the analog hard macro blocks like any other digital hard macros.

Probably someone working on a mixed-signal project with a more critical analog block in the design would have more requirements like shielding adjacent metal layers & power rings perhaps?

 

[kolla]

Thanks again cop02ia for the great answer. Your experience was indeed
helpful to expand my knowledge here. I heard the SOCE has an integrated
"Analog" router which apparently is intended to be used with mixed signal
designs. But since SOCE is a digital platform I wonder how this is used
in practise. If I'm just bringing in a Analog Hard Macro would there be any
use of such a router? Or is this Analog router intended to be used in other
situations??
I'm not familiar with mixed signal designs so I may have missed some basic concepts there..