SOC Encounter CTS - *ERROR: No sync pins are in clock uPAD_M

[george100]

SOC Encounter CTS

I get this error when I try to synth clk in GUI:

Tracing Clock uPAD_MDQ_clk/OY ...
*** End Tracer (mem=129.8M) ***
**ERROR: No sync pins are in clock uPAD_MDQ_clk/OY. Please remove it from clock spec file.

This is how I created the clock in SDC:
create_clock -name {IO_MEM_NPL_MDQ_Y_clk_} -period 20.000 -waveform { 0.000 10.000 } [list [get_pins {uPAD_MDQ_clk/OY}]]

makes no diff when I set ON/OFF: setIoPinAsSync, setDPinAsSync

plz help,
thanks

 

[svr]

Re: SOC Encounter CTS

could you try tracing this pin uPAD_MDQ_clk/OY in the preCTS def/nl.
i suspect, there are no flops connected to this pin. in that case, CTS would certainly fail to trace clock from this port.

 

[george100]

Re: SOC Encounter CTS

I found the problem.
The flops were not declared in the timing lib.
The cells in the lib have some enable/disable statements, like:

dont_use: true;
clock: true;

All these must be verified visually. I spent a few hours scratching my head till I found this silly mistake.

thanks,
george

Added after 2 hours 53 minutes:

I synthesized the clock. However the tool dumps two contradictory messages below:

Start to trace clock trees ...
*** Begin Tracer (mem=122.2M) ***
**WARN: Find clock buffer IO_MEM_NPL_MDQ_Y_clk___L1_I0 in the clock tree.
**WARN: Clock uPAD_MDQ_clk/OY has been synthesized.
*** End Tracer (mem=122.2M) ***
**WARN: No clock tree has been synthesized.
*** End ckSynthesis (cpu=0:00:00.1, real=0:00:00.0, mem=119.2M) ***

QUESTION: shoud I ignore msg: "No clock tree has been synthesized" ?
The netlist dumped after clock synthesis DOES have the clock tree nets&BUFs: chip_cts/chip_cts.v

Also the clock has NOT been routed after using GUI sequence:
1) Menu/Clock/Create_clock_tree_spec
2) Menu/Clock/Specify_clock_tree
3) Menu/Clock/Synthesize_clock_tree

QUESTION: is it expected that the clock nets are not routed at this point?

But after I do Menu/Route/NanoRoute, I can see the clock tree nets&BUFs in the layout.

 

[cadinfo]

Re: SOC Encounter CTS - *ERROR: No sync pins are in clock uP

Hi, george100,

Did you find out the root cause of your CTS issue?

Recently, I got the same messages,

Start to trace clock trees ...
*** Begin Tracer (mem=1372.0M) ***
**WARN: (ENCCK-767): Find clock buffer module_clk__L1_I0 in the clock tree.
**WARN: (ENCCK-209): Clock module/inst/xan/Y has been synthesized.
*** End Tracer (mem=1372.0M) ***
**WARN: (ENCCK-719): No clock tree has been synthesized.

Thanks.

 

[shelby]

I think I have seen the same warning message before and ingnored it. Check you tree pre and post CTS to see if it makes sense using the Clock -> Clock Tree Browser GUI

Normally your clock nets are not routed during CTS and get routed when using NanoRoute. I think the command is "RouteNet true" you can put in your clock spec file (.ctstch) to force the route to be done during cts.