Slew rate on Razavi's book

[prcken]

Hi, I was reading from Razavi's analog book about the slew rate for two-stage diff-pair input topology.
I am confused about the positive slew rate description. as you can see the attached.


in fig. 10.34 (b), I think during Vin from 0 to VDD, voltage at node X is decreasing to almost zero and triodes the tail current Iss, so that Iss will be almost 0, too. M5 doesn't need to provide that Iss to charge Cc, so that there is no Iss current source limiting the slew rate once the size of M5 is large enough.

if I can make output stage as class AB, there will be no slew rate limitation at all.

My understanding correct? any comments are welcome, thanks!


okay, i think i am wrong, this is configured as a buffer, M2 is not off during slewing so that Iss is there, but seems limited only by a fraction of Iss. it's hard to visualize it dynamically

 

[nature0303]

Hi,prcken
I think when Vin is high enough to reach Vdd,M1 is triode,and the Drain voltage of M1 is about the value of the drain voltage of vss(mostly a biased NMOS),then,node X is pull down,and the current cross M5 increases,which result in the increase of the Voltage of the Drain of M5,so the gate voltage of M3,M4 increase and turn off M3,M4.So,the all the Iss should be compensate from M5.Is that clear?

 

[prcken]

hi nature0303,
thanks. but still not very clear to me. slewing happens before vin reaches VDD. and actually if you really simulate, node X won't go down to vss.