Sizing of CMOS level shifter

[terebin4]

Hi,
can anybody explain how I do sizing of CMOS level shifter by cross coupled pmos transistors.

The model file is attached and I want to shift level 1.8 to 3.3 volts.

Thanks

 

[dick_freebird]

You size by result. NMOS needs to be able to overdrive the PMOS
and sometimes you see drain resistors attached to the PMOS to
get a better speed balance LH - HL and side-side.

Look for minimum and balanced propagation delays across the
envelope (P,V,T) without violating some leakage or size constraint.

 

[erikl]

Hi, can anybody explain how I do sizing of CMOS level shifter by cross coupled pmos transistors.

If you want a suggestion to start with: Use (W/L)PMOS / (W/L)NMOS = U0NMOS/U0PMOS ≈ 2.4 (from your TSMC 0.18um SPICE file) and min. L (for a fanOut up to ≈5). Then try and optimize as dick_freebird suggested above.

 

[terebin4]

Thanks to all..for their suggestions..
.