Size of integrated circuit

[hanen88]

Hi
I would like to calculate the size of overall integrated circuit without doing layout. The proposed circuit included several integrated circuits (NMOS and Pmos transistor). How can i determine theoretically the overall size . I'm so gratefull if you help me.
Best regards

 

[dick_freebird]

The core sounds trivial but not quantified. This
is a quantitative problem.

For a testable chip there will be bonds pads
about the periphery. You can expect the I/O
and power ring to take 100um (small pads)
to 200um (HiRel, big wedge-bond aluminum
pads). This adds to the core dimension.

For a rough stab at core, count the transistors,
assume they are maybe 2-4X minimum (for
drive) width, min length, measure the butted
extents or add fudge factors to X and Y (W and L)
for active-to-everything. Do the area arithmetic.
Now double it for a low-metal-layers-count,
maybe add 50% for 4 layer, 25% for 6 layer
routing (packing improves with layer count).
Take square root for dimension, from area. Add
pad ring. Add maybe another 100um for two
half-scribe lanes, to X and Y.

Now that's probably as good as it gets without
somebody pushes a puck for a while.

 

[hanen88]

Hi Sir,
I understand that the dimension of each transistor is W*L; after that i summed all size of used transistors.
I used technology TSMC 0.18 µm (6 layer). So, i should add 25% of the calculated size to have the overall size ( it means i should take account the size of routing). Please to clarify more how to calculate the overall size.
Best regards