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Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 LIBRARY IEEE; USE ieee.std_logic_1164.all; --USE ieee.std_logic_arith.all; USE ieee.numeric_std.all; library ieee_proposed; use ieee_proposed.fixed_pkg.all; ENTITY dwt IS PORT ( clk : IN STD_LOGIC; vid_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Pixels from main memory hor_sync: IN STD_LOGIC; -- Horizondal synchronous pulse vert_sync: IN STD_LOGIC; -- Vertical synchronous pulse val_flag: IN BIT; -- Flag indicates valid pixels vid_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); v_out: OUT STD_LOGIC; h_out: OUT STD_LOGIC; val_out: OUT STD_LOGIC ); END dwt; ARCHITECTURE dwt_behaviour OF dwt IS TYPE buf_ary IS ARRAY(NATURAL RANGE <>) OF UNSIGNED (8 DOWNTO 0); TYPE buf_ary_1 IS ARRAY(NATURAL RANGE <>) OF SIGNED(7 DOWNTO 0); TYPE buf_ary_dd IS ARRAY(NATURAL RANGE <>) OF sfixed (3 DOWNTO -3); TYPE buf_ary_d IS ARRAY (NATURAL RANGE <>) OF sfixed (4 DOWNTO -9); --Internal Buffers SIGNAL buffr: buf_ary_1(99 DOWNTO 0 ):=(OTHERS=>(OTHERS=>'0')); -- Internal Buffer into which pixels will be loaded SIGNAL buffo: buf_ary (99 DOWNTO 0 ); -- Internal Buffer into which pixels will be stored SIGNAL d : buf_ary_dd (102 DOWNTO 0):=(OTHERS=>(OTHERS=>'0')); SIGNAL dd : buf_ary_d (102 DOWNTO 0):=(OTHERS=>(OTHERS=>'0')); SIGNAL data_in: STD_LOGIC_VECTOR(7 downto 0); SIGNAL shift : BIT:='0'; --Control signal to manage the row caches SIGNAL flush_pip:BIT:='0'; --Control signal to omit first and last column SIGNAL ready : BOOLEAN:=FALSE; -- Controll signal to manage output of the system SIGNAL temp1: sfixed (3 downto -3); SIGNAL temp: sfixed (3 downto -3) ; SIGNAL i : integer := 0; SIGNAL s : buf_ary (102 DOWNTO 0):=(OTHERS=>(OTHERS=>'0')); signal temp2 : sfixed(4 downto -9); SIGNAL row : buf_ary_1(2 DOWNTO 0); --row Cache SIGNAL res_row : SIGNED(7 DOWNTO 0); --SIGNAL res_row : buf_ary(3 DOWNTO 0); --Result row Cache --Status signals SIGNAL col_res : INTEGER; -- Total columns SIGNAL row_res: INTEGER; -- Total Rows SIGNAL fin:BIT:='0'; --Internal status signal showing end of frame signal b : sfixed(0 downto -6); signal sgn : signed(7 downto 0); BEGIN --************************* Represents the buffering of incoming frame in DDR3 Memory (transfers pixels from vid_in to buffr)***** buff : PROCESS(clk) VARIABLE index: INTEGER :=0; VARIABLE row_cnt: INTEGER:=0; VARIABLE col_cnt: INTEGER:=0; VARIABLE col_tr: BOOLEAN:=FALSE; BEGIN IF CLK'EVENT AND (CLK='1') THEN IF (val_flag='1') THEN --buffr(index)<=('0' & UNSIGNED(vid_in)); --transfers pixels from vid_in to buffr sgn <= signed(vid_in); buffr(index)<=(sgn); index:=index+1; IF (col_tr=FALSE) THEN col_cnt:=col_cnt+1; END IF; END IF; --If horizontal synchronous pulse is 1, it is the end of the row IF (hor_sync='1') THEN row_cnt:=row_cnt+1; IF (col_tr=FALSE) THEN col_res<=col_cnt; col_tr:=TRUE; END IF; END IF; --If vertical synchronous pulse is 1, it is the end of the column IF (vert_sync='1') THEN row_res<=row_cnt; --row_cnt:=0; col_cnt:=0; index:=0; END IF; END IF; END PROCESS buff; dwt_i:PROCESS(clk) VARIABLE j : integer := -2; VARIABLE i1 : integer := 2; VARIABLE i2 : integer := 0; VARIABLE a : integer := 1; BEGIN IF(clk'EVENT AND clk='1') THEN IF ( vert_sync ='1') THEN row(2 downto 0) <= buffr((i1) downto (i2)); j :=j+1; i1 := i1+2; i2 := i2+2; i<=j+1; a := a+1 ; END IF; END IF; IF(clk'EVENT AND clk='1') THEN IF a /= 4 THEN temp1<= to_sfixed( (row(1)-((row(0) + row(2)) srl 1)) ); ELSE temp1 <= to_sfixed (row(1) - row(0)); a := 0; END IF; END IF; END PROCESS dwt_i; d_assign: PROCESS(temp1) begin b <= to_sfixed (0.703125,b); temp2 <= temp1 * b; d(i)<= (temp1(3)&temp1(2)&temp1(1)&temp1(0)&temp1(-1)&temp1(-2)&temp1(-3)); dd(i)<= (temp2(4)&temp2(3)&temp2(2)&temp2(1)&temp2(0)&temp2(-1)&temp2(-2)&temp2(-3)&temp2(-4)&temp2(-5)&temp2(-6)&temp2(-7)&temp2(-8)&temp2(-9)); END PROCESS d_assign; END dwt_behaviour;
the code doesnot show any error but the simulation stops after 1 clock...
what is the problem ?
thanks in advance