Simulation problem of a classical PI controllers using op amp for buck converters

[Sciebou]

Hello,

I would like to simulate a buck converter in closed-loop with SABER. Here is the schematic:


Classically, there are two loops with PI controllers: external voltage loop, and internal current loop. The output of the current loop's PI controller is compared to a sawtooth signal in order to generate PWM signals for gate drive.
Vin = 270V
Vout_setpoint = 30V
Rload = 1.8V
fsw = 400k
time step = 0.5u

However, I obtained the following strange results:
Output voltage:

The two op amp are both saturated. (Vcc and Vee are increased to ±30V, which is very big, but if not Vout is very small).

The MOSFET's and diode's current are strange, the PWM signals as well:


Finally, the diode's cathode voltage is not as expected. Its maximum is normally Vin = 270V, but is limited here to 28V::-(


PI parameters are carefully calculated with these two transfert functions:


Do you have some diagnosis for my problem?
Many thanks for your help.

 

[BradtheRad]

fsw = 400k
time step = 0.5u

Your timestep creates 5 steps per cycle. This is unlike the simulator that I'm familiar with, which requires a higher number of steps per cycle. Therefore a suitable timestep is more like 10 nSec. I don't know for certain whether that is the cause of your odd results.

- - - Updated - - -

Vin = 270V
...
Rload = 1.8V

This implies a very short duty cycle, 1 or 2 percent. It may be more practical for you to set the output voltage to a higher value, and see if that creates the waveforms you expect.

Also your output capacitor appears to have a value of 92 mF, or 92,000 uF. This could require many cycles before it charges to normal operating level.

 

[Sciebou]

Hi BradtheRad,

Thank you for your idea.

I've thus reduced the time step to 100n, because at 10n and even 50n, SABER seems to have some difficulties to find numerical solutions at the beginning of the simulation.

But a smaller time step doesn't change the problem. The evolution of Vout is the same. The MOSFET's current is still strange:


Regards.

- - - Updated - - -

Vin = 270V Rload = 1.8V This implies a very short duty cycle, 1 or 2 percent. It may be more practical for you to set the output voltage to a higher value, ...

Sorry about this mistake, I should write Rload = 1.8ohms instead of 1.8V. Otherwise, my output voltage is actually 30V.

your output capacitor appears to have a value of 92 mF, or 92,000 uF. This could require many cycles before it charges to normal operating level.

Yes, I reduced C 1000 times in order to see how change the results, but it only affected the transient response and not the steady state:

 

[FvM]

Your gate driver circuits limits the output voltage to below 30 V, independent of the input voltage. The output voltage can't reach the setpoint and the voltage controller is in saturation.

You need to redesign the gate driver circuit.

 

[Sciebou]

Hi,

Thank you FvM for your answer and advice! I added a non-isolated totem-pole gate driver for the switch as in the figures below (with VDRV = 350V as Vin = 270V)



Unfortunately, my schematic still doesn't work properly. There is the following warning message: "The no_ramping algorithm failed. Trying the dyn_ramping algorithm." I did wait long time but the simulation didn't begin to be launched. It's bugged!

Do I make mistakes or miss essential things in this gate driver design and/or connection? (Knowing that this is an inverting driver, I've already inverted the PWM controller's output).

Thank you very much in advance for your help.

Sciebou.

 

[FvM]

Do you know that MOSFETs have maximum Vgs rating of eg. +/- 20 V? Apart from possible simulation problems, your driver circuit will never work with real MOSFETs.

 

[treez]

SABER is a private proprietory software for which no quick start guide exists...you get to know saber by being "in the know".
Here is a buck with a PI loop in the free LTspice, a simulator for which there is loads of web help
SABER also costs a small fortune.

At the end of the day, if you are not capable of doing stuff like state space model calculation of gain and phase margin (and please forgive me if you are capable of this) , then whats the point of using saber?...just use ltspice instead.

Of course, anybody in the "saber clique", will tell you that ltspice is useless....trashing other engineers so as to further themselves and make themselves look better, worth more money.

 

[Sciebou]

Thank you FvM for your quick feedback.
You are right. VDRV was huge and it has to be reduced.
However, I've seen in this article: http://www.radio-sensors.se/download/gate-driver2.pdf, that for high side gate drivers, there are the following conditions:

VDRV < VGS,max
VIN < VDRV - VGS,Miller

As in my circuit, I would like to have VIN = 270V. It seems not to be possible, see these above conditions.
Do you have some ideas how to design a gate driver in this case (with a very high VIN)?
Thanks a lot for your help!

 

[dick_freebird]

A simple vcvs can transfer a gate drive voltage signal to a
flying high side. You won't have realism unless you add some
series resistance and so on. You could drive a dummy FET
at the low side and pick off its V(g,s) waveform and apply
it to the high side FET via vcvs.

Your problem statement doesn't include designing a gate driver
in detail, as far as I can see - just get the job done.

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Of course, anybody in the "saber clique", will tell you that ltspice is useless....trashing other engineers so as to further themselves and make themselves look better, worth more money.

Yeah, maybe 20+ years ago I had some discussions with a
Saber apps engineer and he went on and on about all of this
stuff he could do the hard way (as I saw it). None of it was
relevant to the work at hand and I never got any more into
it. Of course no other simulator could do all of that irrelevant
stuff the hard way and he was mighty proud of that. But two
or more decades down the road, it's still pretty much a niche
tool that people only use because it's what they're told to.