Simulation of Xilinx cores (ie. FIFOs)

[Richard29]

Hi all,



I am trying to incorporate the Xilinx HWICAP controller into my design. The problem I face now is that I need someway

to simulate a FIFO that is generated with the FIFO Generator v6.1 as follows:

COMPONENT fifo_generator_v6_1
  GENERIC (
    C_COMMON_CLOCK           : integer := 0;
    C_COUNT_TYPE                  :  integer := 0;

   ...

 )

  PORT(
    CLK                       : IN  std_logic := '0';
    BACKUP                    : IN  std_logic := '0';

 ...

)

 

ATTRIBUTE box_type : STRING;
ATTRIBUTE box_type OF fifo_generator_v6_1 : COMPONENT IS "black_box";

ATTRIBUTE GENERATOR_DEFAULT : STRING;
ATTRIBUTE GENERATOR_DEFAULT OF fifo_generator_v6_1: COMPONENT IS
"generatecore com.xilinx.ip.fifo_generator_v6_1.fifo_generator_v6_1 -a map_qrvirtex4_to=virtex4 map_qvirtex4_to=virtex4";

Of course when I just simulate my design this is a blackbox. But to see that I got everything right, I would need to be able to

simulate this core. Is there a simple way to do that? I assume I have to manually generate this core and then incorporate it in some way in my design. Some guidance what be great how best to proceed with this matter.


Many thanks!