Simulation of particle swarm optimization

[felix965]

implementation of PSO on fpga

anyone can suggest me for how to convert this code to verilog code

for iter = 1:maxIter
    swarm(:, 1, 1) = swarm(:, 1, 1) + swarm(:, 2, 1)/1.3;
   swarm(:, 1, 2) = swarm(:, 1, 2) + swarm(:, 2, 2)/1.3;
    x = swarm(:, 1, 1);  
   y = swarm(:, 1, 2); 
  fval = objfcn([x y]);

with regards
R.FELIX ANAND

 

[ads-ee]

Re: implementation of PSO on fpga

What does PSO stand for (maybe it is Phenomenally Silly Obfuscating...acronym?)

Never use an acronym unless it is ubiquitous outside your field of expertise. Like IC, RAM, CGI, DSP, etc, which people outside of those disciplines and even quite a few people who are not even engineers may know something about these terms.

Also what is this supposed to be? swarm, 1, 1)
Off hand, I don't recognize this syntax. I assume this one is an array of some sort: objfcn([x y]).

anyone can suggest me for how to convert this code to verilog code

I suggest if you want to convert the code to Verilog you first understand the algorithm you have above, then learn Verilog is not a programming language but is a Hardware Description Language, so you are designing with flip-flops (FFs), gates, and memories. Unless you know what the FF and gate circuit looks like you will have a much more difficult time describing it in Verilog and will likely end up with a Verilog program that will synthesize to really poor performing hardware. You also don't have arrays in hardware, if you want an array that means you have to design hardware that treats a memory as an array.

 

[bking]

Re: implementation of PSO on fpga

What does PSO stand for (maybe it is Phenomenally Silly Obfuscating...acronym?)

I'm going to guess Particle Swarm Optimization. It's a Computer Science concept. The 'swarm' and 'iter' (iteration) lean that way.

There are some things better left to processors.

 

[dpaul]

Re: implementation of PSO on fpga

I had ignored this post earlier due to the apparently unclear question.
Probably the OP wants an easy way to translate some Matlab code into Verilog.

 

[felix965]

hi everyone,


i have small error while simulating this vhdl code.in modelsim 6.4a verision

anybody can rectify my problem.

"Declaration with designator "cp2" already exists in this region"

 

[vGoodtimes]

First, you don't have the full loop. As a result I will declare you can replace the loop by a constant multiplication.


"cp2" already exists means you have declared two things "cp2" in the same scope in a way not allowed by VHDL.

search your code for "cp2". You are declaring something twice. Or you have to process/block/etc... in the same scope with the same name.