mahmood.n
Member level 5
I wrote a T latch with concurrent statements in VHDL
As I simulate this code with active-hdl, I get this error
I increased the value from 5000 to 10000 but still get the same error.
Any idea?
Code:
entity tlatch is
port( t, e: in bit;
q, qb: inout bit);
end;
architecture x of tlatch is
signal o1, o2: bit;
begin
o1 <= t and e and q;
o2 <= t and e and qb;
q <= o1 nor qb;
qb <= q nor o2;
end;
As I simulate this code with active-hdl, I get this error
Code:
# KERNEL: Stopped at time 0 ps + 10000.
# KERNEL: Error: KERNEL_0160 Delta count overflow. Increase the iteration limit using -i argument for asim or the matching entry in simulation preferences.
Any idea?