mchengh
Newbie level 3
How to avoid race condition on RTL and Netlist mixed simulation
Hi,
Currently we have met some race conditions when doing RTL + Netlist simulation using irun, where RTL is the top module and some blocks are Netlist.
We tried +delay_mode_unit and +delay_mode_zero option, and still fails.
Whether there're guidelines for this kind of simulation, eg. how to avoiding race conditions in-between RTL and Netlist block interface ?
ps.
The below thread has the similar title but not state the same thing.
https://www.edaboard.com/showthread.php?t=266399
Thanks for your help.
Martin
Hi,
Currently we have met some race conditions when doing RTL + Netlist simulation using irun, where RTL is the top module and some blocks are Netlist.
We tried +delay_mode_unit and +delay_mode_zero option, and still fails.
Whether there're guidelines for this kind of simulation, eg. how to avoiding race conditions in-between RTL and Netlist block interface ?
ps.
The below thread has the similar title but not state the same thing.
https://www.edaboard.com/showthread.php?t=266399
Thanks for your help.
Martin