simulation error in cadence virtuoso tech file related ( probably)

[yans123]

Hi ,

For university project , I used PTM spice model model for 45 nm technology.

when I left the width and length of the transistors empty .
The results were not good but ths simulation ran fine .
after I tried inserting values ( let say L=45n , w=45nm)
I got the error :
the parameter `xgl` must be smaller than `Ldrawn + Lmlt + XL = -20nm

Does anyone has any idea what may be the problem ?

Thanks ...:shock:

 

[jpvSoccer]

Hi,

Could it be that L=W=45 is violating a constraint in your model?

Have you tried other combinations of L and W?

Does it make sense to have the length equal to the width equal to the minimum drawn size for your technology?

 

[shravan87]

Try looking at the model documentation, to see the minimum length allowed.

Also, you can look at the layout documentation if any, to look at minimum possible length, width etc.

Try L=50nm (If you are using the NCSU PDK).