Simple PCM clock recovery

[domble]

Got an NRZ PCM data stream, need to recover a clock from it.

The PCM data is via a radio channel.
Using an integrate-and-dump filter to recover the actual data from the PCM, so the clock is used to time this.

Using a rectifier, ringing filter, and PLL works well, but...

The data rate may vary by about 10% (slowly, only temperature variations).
(The recovered clock is also used by the decoding PIC to adjust its own clock rate to match the data rate, recovered data is actually input via the UART). A ringing (LC) filter can't handle these large variations in clock rate.

So, we've tried different types of phase detectors which don't mind missing edges (i.e. PCM data). Now we can't get the PLL to lock over the full input frequency range using alexanders or hogge phase detector, unless it is also very sensitive to noise and jitter on the input data.

Any suggestions for loop filter types? Active integrating loop filter seems best (allows zero phase shift from hogge detector) but making it actually work is difficult.

2µs bit time, 74HC4046 VCO. PCM data from PIC, 'idle' periods of about 10 bit times max. Bit clock is continuous (i.e. doesn't change phase between tx bytes).

Someone point me towards a good resource?

dom.

 

[artem]

may be it is stupid idea - can you autotune the ringing filter (by varicaps) ?
And/or may be you can add some frequency retention facility to your circuit that it will keep latest freq if there wont be input from ring filter or another cdr variant. That will ensure lock will be there after 10 bits duration gap.

 

[domble]

may be it is stupid idea - can you autotune the ringing filter (by varicaps) ?

Not a stupid idea! Probably could, had wondered about that. But the pic micro would have to control the varicap, adjusting it to peak the p-p voltage output from the filter. Could be a tricky algorithm, because it would have to work out which way to adjust the varicap (could be tuned to either side of peak...).

And/or may be you can add some frequency retention facility to your circuit that it will keep latest freq if there wont be input from ring filter or another cdr variant. That will ensure lock will be there after 10 bits duration gap.

Think a really slow responding PLL loop filter would do that, but that seems to need a phase/frequency detector (I think the type 2 in the 4046 is) to enable a good capture range.

I was also wondering if there are any digital / software techniques... but I think that'd need relatively fast clocks.

This is the easy one first, the other system is 2MBit pcm data (4 times faster).

dom.

 

[ridamsahu]

you can use PLL for that............