Shift Register 74165-74164

[krayzee]

Hi All,

I am trying to connect a 4 bit signal to 74165 to convert to serial, then a 74164 to convert back to parallel on EWB.

I am having issues getting the correct signal out. I have tried numerous options, but don't seem to have found the right combination.

Any pointers would be gratefully appreciated.

 

[barry]

1) there's nothing connected to SH/LD
2) there's nothing connected to CLK
3) you've got a 10KHz signal connected to the INHIBIT input.
4) you've got no timing diagrams showing what you expected, or what you're getting.

 

[FenTrac]

Looking at the wiring diagram, the data is going into the 74165 on A,B,C,D parallel inputs. It will take 8 clock pulses for this data to be completely shifted out on QH, the A data bit being the last to leave. On the 74164 the data is shifted onto QA,QB,QC,QD outputs after being shifted into the A serial input. It will take 8 clock pulses to arrive there, the A data bit being the last to arrive. Providing that the 2 shift register's clocks are coodinated so the 74164 is clocked when valid data is available on the A input. That is all that can be stated from the diagram since nothing is known about any of the control signals, interface devices, etc.

 

[krayzee]

Hi FenTrac,

The full circuit is as follows: I am trying to transmit the signal from a generic ADC to a 74154 4 Line to 16 Line Demultiplexer over a serial line. The circuit works without the intermediary shift registers.

Many Thanks,

 

[KlausST]

Hi,

What a chaotic schematic.
It will be hard for yourself to read....but for us even more.

Avoid crossings, keep distance, use GND symbols.

For the problem itself.
Just shifting bits out and in gives nonsense results. You need to synchronize both serial streams and you need some kind of frame sync.

(Example without framesync
ndombeginningWithoutaframesyncthebitstreamhasnostartnoendandnoordertheywillbeshiftedthroughtheoutputwithoutbytealignmentrandomen

"Space" is nothing. But you see how useful a "space" is as word sync, or a "." as sentence sync
And how useful special characters like "capital letters are"
There is no need to re invent the wheel. There are a lot of standard communication interfaces.

(Example without bit sync)
,$£:/7fuv/}ID&Uu♡■ .....and so on

--> total nonsense output

Read through UART, SPI, I2C.....
All are parallel to serial and back, all have dedicated ways to "sync" bytes and frames.

Klaus

 

[FenTrac]

There needs to be some method of controlling the shift register clock and control inputs. For example pin 1 of the 74165 is shown tied to ground in the schematic. According to the datasheet when pin 1 is low, parallel data is entered but shifting is inhibited. So according to the schematic the shift register can't operate. So, you need to be changing the pin's state to control the shift register operation.
Like wise, the schematic shows pin 15, (clock 2), tied high. According to the datasheet, if it is high the shift register will not shift, it needs to be low.
Also as mentioned earlier and pointed out by Klaus the clocks of the 2 shift registers need to be coordinated so they are each shifted 8 times in sequence for valid data to be sent, and then stopped so the data is stable to display. Start by studying the datasheets and then come up with some way to control the shift register clocks and control signals.

 

[barry]

Redraw your schematic!!!!! I understand that you may be new at this, but what a mess. You can't run wires across a device! You've got unnecessary loops and just no thought went into drawing this.

AND you've got your INHIBIT pin pulled high which will INHIBIT THE SHIFT REGISTER FROM DOING ANYTHING!!!

 

[krayzee]

Many thanks for the responses, and feedback regarding the chaos of my diagram - I have tried to tidy it up. Unfortunately whenever anything is moved, EWB arbitrarily relocates all the connections into a bowl of spaghetti.

Also EWB doesn't include microcontrollers that can implement UART, SPI, I2C - I think.

Am I right in thinking that I will require additional components such as a 555 timer to sync the frames?

 

[FenTrac]

Yes, it will take some additional components to sync the frames. It would be good to start with a sequence of events that need to take place.
At the beginning of each frame the SH/LD pin 1 needs to be brought low and then high to load the parallel data into the shift register. INH pin 15 needs to be LOW for the 74165 to shift. Then each shift register needs 8 clock pulses to shift the data out. The 74165 needs to be clocked before the 74164 so that there is valid data from the 74165 at the 74164 serial input A pin 1 at the time it is clocked. After 8 clock pulses the parallel data on the 74164 needs to be stable to read the 64154 output. This could be done by stopping the shift register clocks or using a latch IC between the 74164 and 74154 to store the data. There are multiple ways to think of how things can be done.