martraf
Newbie level 2
I want to share same SDRAM memory with FPGA and ARM(with SDRAM controller). First FPGA will fill memory, then ARM will read it. It will be long cycles, for examples 10000 read/writes (no rapid switching bus master). Can I do it without bus buffers like 74ALVCH16245? Will it be dangerous for elements? My idea is to simply add 2 communications lines beetwen FPGA and ARM(bus_request and bus_granted)
Sorry for my poor english.
Sorry for my poor english.