Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Sharing SDR SDRAM with FPGA and ARM

Status
Not open for further replies.

martraf

Newbie level 2
Newbie level 2
Joined
Sep 9, 2007
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,294
I want to share same SDRAM memory with FPGA and ARM(with SDRAM controller). First FPGA will fill memory, then ARM will read it. It will be long cycles, for examples 10000 read/writes (no rapid switching bus master). Can I do it without bus buffers like 74ALVCH16245? Will it be dangerous for elements? My idea is to simply add 2 communications lines beetwen FPGA and ARM(bus_request and bus_granted)

Sorry for my poor english.
 

How do you want to generate the handshake signals at the ARM side? Even if you stop SDRAM accesses in ARM software, the SDRAM controller would still perform periodic refresh, possibly conflicting with accesses from FPGA.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top