Sharing SDR SDRAM with FPGA and ARM

[martraf]

I want to share same SDRAM memory with FPGA and ARM(with SDRAM controller). First FPGA will fill memory, then ARM will read it. It will be long cycles, for examples 10000 read/writes (no rapid switching bus master). Can I do it without bus buffers like 74ALVCH16245? Will it be dangerous for elements? My idea is to simply add 2 communications lines beetwen FPGA and ARM(bus_request and bus_granted)

Sorry for my poor english.

 

[FvM]

How do you want to generate the handshake signals at the ARM side? Even if you stop SDRAM accesses in ARM software, the SDRAM controller would still perform periodic refresh, possibly conflicting with accesses from FPGA.