setup time is less than hold time,will this cause problem???

[gauz]

Hi all,

below is part of the twr file, we can see that the setup time is much less than the hold time, this means the input clock delay is much greater than the input data delay,

will this case any potential problem? the interface is a standard pci interface and connected to pci board on pc slot by a ribben connector which will introduce about 3-4 ns delay.

I assign the input clock pci_clk from a local clock pad rather than a global clock pad, which I think introduced much clock skew and I didn't set any io constraints to the interface.

the pci_clk runs at 33Mhz.



is this timing reasonable? is there any step could I take to improve the timing?



thanks



Setup/Hold to clock pci_clk
---------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
---------------+------------+------------+------------------+--------+
io_a_pad[0] | 0.153(R)| 4.806(R)|pci_clk_int | 0.000|
io_a_pad[1] | 0.137(R)| 5.237(R)|pci_clk_int | 0.000|
io_a_pad[2] | 0.142(R)| 6.642(R)|pci_clk_int | 0.000|
io_a_pad[3] | 0.181(R)| 6.327(R)|pci_clk_int | 0.000|
io_a_pad[4] | 0.169(R)| 6.374(R)|pci_clk_int | 0.000|
io_a_pad[5] | 0.211(R)| 6.310(R)|pci_clk_int | 0.000|
io_a_pad[6] | 0.204(R)| 6.306(R)|pci_clk_int | 0.000|
io_a_pad[7] | 0.193(R)| 6.349(R)|pci_clk_int | 0.000|
io_a_pad[8] | 0.189(R)| 5.924(R)|pci_clk_int | 0.000|
io_a_pad[9] | 0.186(R)| 6.159(R)|pci_clk_int | 0.000|
io_a_pad[10] | 0.178(R)| 6.098(R)|pci_clk_int | 0.000|
io_a_pad[11] | 0.194(R)| 5.912(R)|pci_clk_int | 0.000|
io_a_pad[12] | 0.189(R)| 5.930(R)|pci_clk_int | 0.000|
io_a_pad[13] | 0.210(R)| 5.889(R)|pci_clk_int | 0.000|

 

[karikalan_t79]

Re: setup time is less than hold time,will this cause proble

i think no problem for fpga, but for asic its problem

 

[edagops]

Re: setup time is less than hold time,will this cause proble

Hi,

Can you explain, How it Impacts the ASIC ?

Thanks

 

[ikki]

Re: setup time is less than hold time,will this cause proble

if there is problem for asic flow, then how do we fix the timing ? .. how do we adjust it ? ..

 

[yx.yang]

I think there is no problem for both FPGA and ASIC, if you set the right input delay constraint. For xilinx FPGA use "offset"; for ASIC, use set_input_delay

 

[ikki]

where do we put the set_input_delay for asic flow ? ... izzit in the netlist ?