no_mad
Full Member level 5
set_case_analysis
Hi all,
My design has inputs from a register. Meaning, these inputs always fix either at 0 or 1. To synthesize this design, can I set these inputs port with “case_analysis” or is it better to set it as false_path??
Please enlighten me..
-no_mad
Hi all,
My design has inputs from a register. Meaning, these inputs always fix either at 0 or 1. To synthesize this design, can I set these inputs port with “case_analysis” or is it better to set it as false_path??
Please enlighten me..
-no_mad