Serious error in Quartus 5.1 (Verilog parameters)

[YUV]

Hi, colleagues!

I have found an error in Q5. It consists in wrong transmitting parameters from Verilog file to upper level.
For example, parameter hex_8_bit = 8'h7f;
Every time then you create a symbol from file, Quartus converts parameters into binary kind.
One exclusion is direct typing of the parameter in decimal kind. In this case conversion is always okay: dec_direct = 999;

The error occurs when parameter exeeds 7 bits.
Please, compare
parameter hex_7_bit = 7'h7f;
parameter hex_8_bit = 8'h7f;

As you can see in the picture, the prefix B is absent, that causes the error.

I have attached QAR archive (zipped) in order to you could check this yourselves.
I believe, my info will help you to avoid problems in your designs. Be careful.

Regards,
YUV

 

[leonqin]

Serious error in qu(at)rtus 5.1 (Verilog parameters)

have you send this to altera MySupport?

 

[YUV]

Sure. They admitted the problem and promised to fix it in the next version.
I would never post this topic if I wasn't sure. At first I sent a message to MySupport. And after I got an answer, I was going to post here.

Regards, YUV

 

[alanj@signalcrafters.com]

Thanks for posting it here YUV.