serial to parallel conversion code in verilog

[ali_bukhari]

anyone who can send me the verilog code for serial to parallel conversion

 

[amraldo]

Try to get the book Verilog Synthesis Primer. You will find a code for a universal shift register.
It has the functionality you are asking.
--
Amr

 

[ali_bukhari]

thx 4 ur reply wud u temme exactly the name of the writer of htis book

 

[amraldo]

https://www.amazon.com/Verilog-HDL-...=sr_1_1?ie=UTF8&s=books&qid=1276165616&sr=8-1

 

[ali_bukhari]

so nice of u kindly lemme kw is it possible to make exact clks of 2 mhz n 8 mhz from 50 mhz system clk ; so that they are synchronized as well

Added after 2 minutes:

do u ve any experience of working on embedded systems?

 

[amraldo]

50 to 2 yes, 50 to 8 no
--
Amr

 

[ali_bukhari]

do u ve any idea of fsm if i send u the fsm code written in verilog would u b able to errect it 4 me?

 

[amraldo]

errect it?!!!!
Do you mean correct it?
--
Amr

 

[umer_366]

ok plz give ur code...

 

[permute]

ali, Look into using DCM's or PLL's for clock logic. The PLL's might only be on a virtex5.

you basically would need to get a 2MHz (or 4MHz) clock, then use a DCM (xilinx) to generate the 8MHz and 2MHz clocks.

 

[ali_bukhari]

but i m using on board system clk of 16 mhz clk this has solved my problems thx 4 ur reply . n do teeme if in any i might help u out