Selecting architecture for an adder in Cadence

[orangelogic]

I am about a make a adder architecutre in cadence using static cmos, can someone suggest a useful resource which can help me in selecting a specific architecture among "carry lookahead" "carry skip" "carry select" and few others.

 

[nozone]

adder architecture

maybe you can synthesize it using digital design flow and import it to virtuoso environment.

 

[giri_lp]

Re: adder architecture

Digital IC's
by JAN Rabaey

will help you fully

 

[anantha_09]

Re: adder architecture

how to import .db file that is gate level net list into virtuso.

 

[gliss]

adder architecture

Try to convert the .db file to verilog or EDIF.

 

[rsrinivas]

adder architecture

i will give u the simplest solution....


module add(a,b,c);
input [15:0]a;
input [15:0]b;
output [16:0]c;
assign c = a + b;
//type in ur architecture details here in a format tat can be understood by DC
endmodule


the gate level netlist is a .v or .vhd file as written by DC.
need more help...?
mail me

Regards
Srinivas

 

[jjftt]

adder architecture

You can refer to
http://www.ecs.umass.edu/ece/koren/arith/slides/
Chapter 5 introduces several kinds of add architecture.

regards

 

[beta0]

Re: adder architecture

You can refer to
http://www.ecs.umass.edu/ece/koren/arith/slides/
Chapter 5 introduces several kinds of add architecture.

regards

good start point, highly recommend