sdf back-annotation warning: conditional delay path

[Robin_zhu]

Hi

I met warnings on the COND path in sdf file can't be annotated to netlist.
all the COND path can't be annotated while others can be annotated.

ncelab: *W,SDFNEP: Failed Attempt to annotate to non-existent path (COND ((A===1)&&(C===1)) (IOPATH B Z)) of instance dbm_tb.u_dbmss.u_dut.SPARE_G_NAND3_1109 of module NAND3X8HXP </proj/DSP/workspace/rzhu/dbm_tb_env/chip/netlist/slow_125c_0p81v.cworst_125.sdf, line 127>

don't know why ... need help ..


Thanks and regards
Robin

 

[mytechface]

paths on SDF should match your verilog model's specify block.

you can try generating SDF without conditional path in case your specify block does not have COND statements.

 

[chipmonkey]

hi,

I also face the same problem described by Robin_zhu.

The condition statements are present in the cell library and SDF file. still the error pops up

BTW, im using VCS. I think the issue is similar

Any help is appreciated.

 

[chipmonkey]

hi,

an update for this issue.
I was facing this issue while by doing the sdf annotation during simulation run time.

Changed this by precompiling the sdf and then ran the simulation and everything were woring fine