Scrambler and Descrambler with FEC

[ali_umair21]

I am using scrambler / Descrambler with FEC for block synchronization in the following manner

Blocks---->FEC Encoder----->Scrambler-------Channel(+err)-------block synchronizer------>Descrambler---->FEC-Decoder--->Blocks

I am using a Burst error correcting cyclic code for this purpose with error correcting capability of 11-bit burst

Now the problem is after syncronization, If n-bits error is added by the channel, Descrambler will multiply this to 3n errors. These 3n errors are well above the the error correcting capability of FEC decoder. Also even for one bit error, Descrambler multiply it to 3 errors beyond the burst of 11-bits

please help me by posting possible solutions to avoid this problem

 

[Sckoarn]

ali_umair21,
In a modem that I worked on, the scrambler was ahead of the FEC block. Basically the scrambler is in place to ensure a good 1's content. So if you are sending a message that is smaller than your bandwidth, you have to pad the message so it fits in your FEC encoder scheme. The scrambler is to randomize your padded 0's. Or that is one reason for scrambling. This should change things.

Sckoarn

 

[permute]

I'm guessing you just have to write the decoder with the descrambler in mind. I'm not sure what exact method you are using. If you are able to detect the location of the first error you should be able to determine how your descrambler's incorrect operation has affected subsequent bits. this will allow you to detect if the next bit is actually in error, in which case you'll be able to correct subsequent bits with this information as well.