fragnen
Full Member level 4
How can scan chains be present inside memories? What are the functionalities of these sequential cells inside a memory so that during DFT these sequential flipflops are replaced by scan flipflops.
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How can scan chains be present inside memories? What are the functionalities of these sequential cells inside a memory so that during DFT these sequential flipflops are replaced by scan flipflops.
I think you got your terminology wrong. Memories don't have flip-flops inside. Classical SRAM memory has bit-cells.
The reason I started this thread is that I also though in your way. The terminology is not wrong.
Are you implying that memory cells are re-used as part of the scan chain? I don't think that is the case. Scan circuitry would be added on top of the existing memory circuit. And as mentioned already, the devices used in memory and in scan chains are not the same.
Memories were purchased from third part and the documents of those memories show scan pins. What scan chains are there inside this memories?
... this is a completely different question from your original question. I suggest you google MBIST, BIST, JTAG, boundary scan, etc. And after that, read the documentation of the purchased memory carefully (I am sure they tell you how to test their memories).
Aware of MBIST, BIST, JTAG. Can you please state what are those scan-in pins for in the memory that are purchased. I do not have the document to read hot those memories should be tested.
I can only make an educated guess that the memory also has some controller logic or buffer that is implemented with flip-flops and that those are tested through a conventional scan chain. The memory bits themselves will NEVER be tested that way, bitcells don't have scan inputs.
But then again, there are so many things that don't make sense in this thread that my guess is a pointless exercise.
That I am aware memory bit cells are not tested through scan chain.
There will be scan cells but they are used to bypass the memory to get controllability and observability of the design