digital design
Junior Member level 2
Hi
I have developed a test bench for my VHDL code and I have generated input file in Matlab. I have saved input file in project file,but simulator can't open it!!
What's wrong?
I have developed a test bench for my VHDL code and I have generated input file in Matlab. I have saved input file in project file,but simulator can't open it!!
What's wrong?