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RS232 to Integrated Interchip Sound (I2S) converter

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robismyname

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I have an application that requires a conversion from RS232 to Integrated Interchip Sound (I2S). Is this a job for an FPGA? Is this feasible?
 

The limitation is rate limit of RS232 , 19200 kbit/s.
Then it depends of clock frequency you need for I2S side.
 

The limitation is rate limit of RS232 , 19200 kbit/s.
Then it depends of clock frequency you need for I2S side.

The I2S clock frequency is 3.077MHz. Please advise.......

---------- Post added at 17:46 ---------- Previous post was at 17:28 ----------

The limitation is rate limit of RS232 , 19200 kbit/s.
Then it depends of clock frequency you need for I2S side.


I found that the I2S clock frequency is 3.077MHz. So does this mean that my RS-232 baud rate can be 3.077Mbps? Is 3.077Mbps an achievable baud rate is serial communication? Please advise if this is at all feasible in FPGA or microcontroller (i.e. 8051) to convert RS-232 to Integrated Interchip Sound Data (I2S).

Thanks.
 

Sorry, there is a typo error. recommended rate of RS232 is 19,2kbits and not 19200kkbits but it seems some devices go to 1,5 MHz.
It is possible to make a bridge but you should be aware you will not have the max speed of I2S possibility.
The data transfert will be slower a expected for a clock at 3,077MHz.
 

In general, no. In specific cases, yes.
you still have possible flow-control issues or clock-data recovery issues.

-- edit:
you really need to define the source of the data. does the data come from a real-time source? does the data come from a stored source? can the data be compressed?

For the sink, you also need to know any performance specs. Also, you need to know if the FPGA provides the clock to the I2S part, or if the clock is provided to the FPGA. besides the I2S clock rate, what is the sample rate and bit-depth that are expected?

These will determine any flow control or sampling rate conversions, as well as allowable buffer sizes, required link rates, ect...
 
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RS232 on PC can run up to 115k baud (2 channels at 16bits with 3kHz sampling), so one can be boost to reach 1.5Mbaud (2 channels at 16bits with 46kHz sampling).
Then a FPGA can easily handle this "conversion" from rs232 to i2s, but the audio sampling will be limited by the rs232 baud rate.
 

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