blackhawk155
Newbie level 4
Hi,
I have problem with using uart macro from xilinx -xapp223 , I've tried to test the marco in activeHDL but it just keep giving me Uninitialized
serial out and buffer full and I don't know what is the problem ? do i have to download some library for activeHDL to use the macro or do any thing else to solve this problem ? !! plz help me if you know
here is my code to test the uart_tx ... i only generate the en_16_x_baud and use the .edn file as component
(note :code is only for simulating .. I'm not gonna implemented in hardware )
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity test is
port (din : in STD_LOGIC_VECTOR (7 downto 0);
write : in STD_LOGIC;
reset_buffer : in STD_LOGIC;
clk : in STD_LOGIC;
serial_out : out STD_LOGIC;
buffer_full : out STD_LOGIC);
end test;
--}} End of automatically maintained section
architecture test of test is
signal clk_div: std_logic ; -- en_16_x_baud is clk_div
signal count_toDiv: integer range 0 to 7 ;
component uart_tx is
port ( din : in STD_LOGIC_VECTOR (7 downto 0);
write : in STD_LOGIC;
reset_buffer : in STD_LOGIC;
en_16_x_baud : in STD_LOGIC;
clk : in STD_LOGIC;
serial_out : out STD_LOGIC;
buffer_full : out STD_LOGIC);
end component;
begin
tx_comp: uart_tx port map(din,write,reset_buffer,clk_div,clk,serial_out,buffer_full);
process(clk,reset_buffer)
begin
if(reset_buffer='1')then
count_toDiv<=0;
clk_div<='0';
elsif(clk'event and clk='1')then
if(count_toDiv=7)then
clk_div<=not clk_div;
count_toDiv<=0;
else
count_toDiv<=count_toDiv+1;
end if;
end if;
end process;
end test;
I have problem with using uart macro from xilinx -xapp223 , I've tried to test the marco in activeHDL but it just keep giving me Uninitialized
serial out and buffer full and I don't know what is the problem ? do i have to download some library for activeHDL to use the macro or do any thing else to solve this problem ? !! plz help me if you know
here is my code to test the uart_tx ... i only generate the en_16_x_baud and use the .edn file as component
(note :code is only for simulating .. I'm not gonna implemented in hardware )
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity test is
port (din : in STD_LOGIC_VECTOR (7 downto 0);
write : in STD_LOGIC;
reset_buffer : in STD_LOGIC;
clk : in STD_LOGIC;
serial_out : out STD_LOGIC;
buffer_full : out STD_LOGIC);
end test;
--}} End of automatically maintained section
architecture test of test is
signal clk_div: std_logic ; -- en_16_x_baud is clk_div
signal count_toDiv: integer range 0 to 7 ;
component uart_tx is
port ( din : in STD_LOGIC_VECTOR (7 downto 0);
write : in STD_LOGIC;
reset_buffer : in STD_LOGIC;
en_16_x_baud : in STD_LOGIC;
clk : in STD_LOGIC;
serial_out : out STD_LOGIC;
buffer_full : out STD_LOGIC);
end component;
begin
tx_comp: uart_tx port map(din,write,reset_buffer,clk_div,clk,serial_out,buffer_full);
process(clk,reset_buffer)
begin
if(reset_buffer='1')then
count_toDiv<=0;
clk_div<='0';
elsif(clk'event and clk='1')then
if(count_toDiv=7)then
clk_div<=not clk_div;
count_toDiv<=0;
else
count_toDiv<=count_toDiv+1;
end if;
end if;
end process;
end test;