Round Robin Arbiter with ring counter

[Abhi3005]

Very urgent.
I would like know that how can we code a round robin arbiter using a ring counter for token generation means if the token is with first user first priority logic 0 will be enabled and so on.Based on the person who is accessing the resource the corresponding value of the person comes as output of priority encoder and will be decoded again in order to get corresponding grant signal.
The design contains :
ring counter for token generation at every posedge of clk which will enable priority logic.
priority logic contains priority encoder and a decoder .
4 request signals are there 4 grant signals at output.
please help me with the code, i am not getting the clear idea as i m a beginner.

 

[TrickyDicky]

What problems are you having with the code?

 

[vGoodtimes]

also, what specifically do you mean? round-robin and priority encoder are two different styles of queuing. I can speculate what some combination might work, but I would only be guessing. For an FPGA, my guess would be that you wouldn't use a ring counter. I guess you could, but in my version of the queuing scheme it would be suboptimal. At this point, I would ask if I understood the queuing scheme correctly and realize that I may not have a full understanding of exactly what you are trying to do.

My guess is aggressive round robin, but the ring counter implementation suggests a slower RR, especially for 4 sources.

 

[Abhi3005]

What problems are you having with the code?

Actually i know how to write code for ring counter, priority encoder,decoder but to write combine code for whole design is diffficult for me as i am new to verilog.

 

[KlausST]

Hi,

is diffficult for me

That´s what happens to everybody.

But explain in detail where is the difficulty.


Klaus

 

[Abhi3005]

Hi,


That´s what happens to everybody.

But explain in detail where is the difficulty.


Klaus

Hi,
Difficulty is implementing in verilog the whole design i know the logic but exactly i m not getting the idea how to write the code for this .

 

[Abhi3005]

the design i want to code is this.

 

[TrickyDicky]

Ok - are you just struggling writing Verilog? There are plenty of tutorials online
Have you even attempted to code this yourself? What problems are you having?
We will not write the code for you.

 

[Abhi3005]

Ok - are you just struggling writing Verilog? There are plenty of tutorials online
Have you even attempted to code this yourself? What problems are you having?
We will not write the code for you.

This is the code i hve written.

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Code Verilog - [expand]
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module arbiter(clk,rst,req,gnt,en);
  input clk,rst,en;
  input [3:0]req;
  output [3:0]gnt;
  reg [3:0]out;
  rc r0(.clock(clk),.reset(rst),.q[0](en));
  prlogic p0(.req(req),.out(gnt),.en(en));
 
  rc r1(.clock(clk),.reset(rst),.q[1](en));
  prlogic p1(.req(req),.out(gnt),.en(en));
  
rc r2(.clock(clk),.reset(rst),.q[2](en));
  prlogic p2(.req(req),.out(gnt),.en(en));
  
  rc r3(.clock(clk),.reset(rst),.q[3](en));
  prlogic p3(.req(req),.out(gntt),.en(en));
endmodule
  
 
// ring counter logic
module rc (clock,reset,q);
  input clock,reset;
    output [3:0] q;
    reg[3:0] q;
 
    always @(posedge clock)
      if (reset)
        q <= 4'b0001;
 
      else
        begin
        q <=  q<<1; 
        q[0]<=q[3];
        end
 
 
  endmodule
 
// priority logic 
 
module prlogic(req,en,out);
  input [3:0]req;
  input en;
  output [3:0]out;
 reg [1:0]x; 
  encoder4_2 e0( .din(req) ,.dout(x),.en(en) );
  decoder2_4 d0( .a(x),.v(out),.en(en) );
  
  
endmodule
 
 
// priority encoder logic
 
  module encoder4_2 ( din ,dout,en );
 
output [1:0] dout ;
reg [1:0] dout ;
 
input [3:0] din ;
wire [3:0] din ;
input en;
 
always @ (din or en) 
begin
if(en)
begin
 case (din)
  1 : dout = 0;
  2 : dout = 1;
  4 : dout = 2;
  8 : dout = 3;
  default : dout = 2'bZ;
 endcase
 end
 else
   
   dout=2'bZ;
end
 
endmodule
 
// decoder logic
module decoder2_4 ( a ,v,en );
 
output reg [3:0]v;
 
input [1:0]a ;
input en;
 
always @(a or en)
if(en) 
begin
v[0] <= (~a[0]) & (~a[1]);
 v[1] <= (~a[0]) & a[1];
 v[2] <= a[0] & (~a[1]);
 v[3] <= a[0] & a[1];
end
 
 
 
else
 
 
  begin
 
 
v[0] <= 1'bz;
 v[1]<= 1'bz;
 v[2]<= 1'bz;
 v[3] <= 1'bz;
 end
endmodule

---

 

[FvM]

There should be only one ring counter instance, driving four separate enable bits. They have to be implemented as wire nets, they can't drive the input en, and you can't have multiple ring counter outputs driving the same net.

 

[Abhi3005]

There should be only one ring counter instance, driving four separate enable bits. They have to be implemented as wire nets, they can't drive the input en, and you can't have multiple ring counter outputs driving the same net.

is this correct ???

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Code Verilog - [expand]
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// arbiter logic
module arbiter(clk,rst,req,gnt);
  input clk,rst;
  input [3:0]req;
  wire [3:0]out0;
  wire [3:0]out1;
  wire [3:0]out2;
  wire [3:0]out3;
  output [3:0]gnt;
  
  reg [3:0]outs;
  wire [3:0]en;
  rc r0(.clock(clk),.reset(rst),.q(en));
 
  prlogic p0(.req(req),.out(out0),.en(en[0]));
 
  
  prlogic p1(.req(req),.out(out1),.en(en[1]));
  
 
  prlogic p2(.req(req),.out(out2),.en(en[2]));
  
  
  prlogic p3(.req(req),.out(out3),.en(en[3]));
 
or a0(gnt[0],out0[0],out1[0],out2[0],out3[0]);
or a1(gnt[1],out0[1],out1[1],out2[1],out3[1]);
or a2(gnt[2],out0[2],out1[2],out2[2],out3[2]);
or a3(gnt[3],out0[3],out1[3],out2[3],out3[3]);
 
endmodule
  
 
// ring counter logic
module rc (clock,reset,q);
  input clock,reset;
    output [3:0] q;
    reg[3:0] q;
 
    always @(posedge clock)
      if (reset)
        q <= 4'b0001;
 
      else
        begin
        q <=  q<<1; 
        q[0]<=q[3];
        end
 
 
  endmodule
 
// priority logic 
 
module prlogic(req,en,out);
  input [3:0]req;
  input en;
  output [3:0]out;
 wire [1:0]x; 
  encoder4_2 e0( .din(req) ,.dout(x),.en(en) );
  decoder2_4 d0( .a(x),.v(out),.en(en) );
  
  
endmodule
 
 
// priority encoder logic
 
  module encoder4_2 ( din ,dout,en );
 
output [1:0] dout ;
reg [1:0] dout ;
 
input [3:0] din ;
wire [3:0] din ;
input en;
 
always @ (din or en) 
begin
if(en==1 | din==4'b0001 | din==4'b0011 | din==4'b0111 | din==4'b1111)
dout=2'b00;
else if(en==1 | din==4'b0010 | din==4'b0110 | din==4'b1110)
dout=2'b01;
else if(en==1 | din==4'b0100 | din==4'b1100)
dout=2'b10;
else if(en==1 | din==4'b1000 )
dout=2'b11;
else
dout=2'bz;
end
 
endmodule
 
// decoder logic
module decoder2_4 ( a ,v,en );
 
output reg [3:0]v;
 
input [1:0]a ;
input en;
 
always @(a or en)
if(en) 
begin
v[0] <= (~a[0]) & (~a[1]);
 v[1] <= (~a[0]) & a[1];
 v[2] <= a[0] & (~a[1]);
 v[3] <= a[0] & a[1];
end
 
 
 
else
 
 
  begin
 
 
v[0] <= 1'bz;
 v[1]<= 1'bz;
 v[2]<= 1'bz;
 v[3] <= 1'bz;
 end
endmodule

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