Kosyas41
Member level 3
Hello,
Im write top level entity for ROM and RAM blocks,I want to connect ROM block with RAM.In ROM block data_a_i and data_b_q I want to connect with data_a and data_b in RAM block.But I faced with error/Could you pls help me to solve this problem
but i have error
Im write top level entity for ROM and RAM blocks,I want to connect ROM block with RAM.In ROM block data_a_i and data_b_q I want to connect with data_a and data_b in RAM block.But I faced with error/Could you pls help me to solve this problem
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use ieee.math_complex.all ;
entity ROMRAM is
port (
CLOC: IN std_logic;
ADD: IN integer range 0 to 511;
DATA_WIDTHi : integer := 256;
ADDR_WIDTHi : integer := 256;
clk : in std_logic;
we_ai : in std_logic;
addr_ai : in std_logic_vector(ADDR_WIDTHi-1 downto 0);
q_ai : out std_logic_vector(DATA_WIDTHi-1 downto 0);
we_bq : in std_logic;
addr_bq : in std_logic_vector(ADDR_WIDTHi-1 downto 0);
q_bq : out std_logic_vector(DATA_WIDTHi-1 downto 0));
end ROMRAM;
architecture rtl of ROMRAM is
--- Component decalarartion
Component sync_rom is
port(
clock: IN std_logic;
address: IN integer range 0 to 511;
data_a_i: OUT integer range 0 to 255;
data_b_q: OUT integer range 0 to 255
);
end component;
Component dp_ram_rbw_scl is
generic (
DATA_WIDTH : integer := 256;
ADDR_WIDTH : integer := 256
);
port(
clk : in std_logic;
we_a : in std_logic;
addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
data_a : in std_logic_vector(DATA_WIDTH-1 downto 0) ;
q_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
we_b : in std_logic;
addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
data_b : in std_logic_vector(DATA_WIDTH-1 downto 0) ;
q_b : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
for all : sync_rom use entity work.sync_rom(rtl);
for all : dp_ram_rbw_scl use entity work.dp_ram_rbw_scl(rtl);
Signal data_a_i: integer range 0 to 255;--interanal signals
Signal data_b_q: integer range 0 to 255;--interanal signals
begin
-- Component Instantiation
C1: sync_rom Port map (
clock => CLOC,
address =>ADD,
data_a_i =>data_a_i,
data_b_q =>data_b_q
);
C2: dp_ram_rbw_scl Port map (
clk=>CLOC,
we_a=>we_ai,
addr_a=>addr_ai,
data_a =>data_a_i,
q_a=>q_ai,
we_b=>we_bq,
addr_b=>addr_bq,
data_b =>data_b_q,
q_b=>q_bq
);
data_a<=to_integer(data_a_i);
data_b_q<=to_integer(unsigned(data_b));
end rtl;
Code:
Error (10476): VHDL error at Vhdl2.vhd(67): type of identifier "data_a_i" does not agree with its usage as "std_logic_vector" type