Rise time and fall time of Inverter.

[Somashekhar]

Hi all,

I have kept NMOS width constant and sweeping PMOS width. Results show that fall time is increasing drastically.

What are the reasons for the increase of FALL TIME?

 

[john blue]

Kr = 1; Kr = Kn/Kp. Kn = UnCox(W/L)n, Kp = UpCox(W/L)p. (W/L)p = 2.5 (W/L)p. This is the characteristic for a symmetrical inverter. If Kr < 1 then the fall time will be slower. If Kr = 1, then it is ideal, if Kr < 1 then it is faster.

 

[Somashekhar]

Thanks john..

Can u tel me physically why the fall time increases..

I think its because Drain capacitance increases as the PMOS width increases..

But i am not sure.. Help me to understand..

 

[john blue]

It is because of the mobility of the electrons and holes which are different. The mobility of electron is 580 cm2/Vs and holes mobility is 230 cm2/Vs. If you derive from the above equation, it is about 2.5 times.

---------- Post added at 08:49 ---------- Previous post was at 08:47 ----------

The effect of capacitance is another factor.

 

[Somashekhar]

John,

My question is "why?" fall time increases when i have kept nmos width constant...

 

[john blue]

Because of the (W/L) which is the width over the length factor. You are changing P MOS width rite? But the Kr changes. It will change the voltage transfer characteristic of the inverter. From there only,you can see the fall time and rise time.