odyseus
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Ring Oscillator
Hi all,
I'm trying to match the theory with a simulation of a three stage ring oscillator using CMOS inverters (ie a P & N device with the gates connected together on the input and the drains connected together on the output).
The theory says you match the W/L ratios (because Kp & Kn are different) to get a symetrical waveform - so far so good.
The oscillating frequency is root 3 times the R-C of a single stage.
The R is equal to 1/(IDS(lambdaN+lamdaP) where IDS is calculated assuming that VDD/2 is applied to each gate.
With my example WP=2um, WN,LN,LP = 1um; Kp = 110E-6 & Kn = 50E-6
VDD=5V, VT = 0.7V
and gives R as ~ 37K so with a 1pF connected as the load the oscillator should work at ~7MHz but ADS simulation shows it working at 40MHz !!
This equates to R being equal to about 4K
Any ideas or any good worked examples ??? :?
Hi all,
I'm trying to match the theory with a simulation of a three stage ring oscillator using CMOS inverters (ie a P & N device with the gates connected together on the input and the drains connected together on the output).
The theory says you match the W/L ratios (because Kp & Kn are different) to get a symetrical waveform - so far so good.
The oscillating frequency is root 3 times the R-C of a single stage.
The R is equal to 1/(IDS(lambdaN+lamdaP) where IDS is calculated assuming that VDD/2 is applied to each gate.
With my example WP=2um, WN,LN,LP = 1um; Kp = 110E-6 & Kn = 50E-6
VDD=5V, VT = 0.7V
and gives R as ~ 37K so with a 1pF connected as the load the oscillator should work at ~7MHz but ADS simulation shows it working at 40MHz !!
This equates to R being equal to about 4K
Any ideas or any good worked examples ??? :?