RF Power Amplifier - DC biasing help.

[xeratule]

Hi,

I'm designing a power amplifier operating at 2.6Ghz. I have the ADS model of the transistor and I choosed 160mA as operating point. When I made DC simulation I saw 4.1V gate voltage is needed at 25V drain voltage. But when I measure the design I see at 3.1V gate voltage, transistor (LDMOS) already drains 160mA current. Is this situation expected? Transistor drains increasingly high current if I increase gate voltage. (Ex: 400mA @ 3.2V gate voltage, 900mA @ 3.3V gate voltage) I can't see any oscillation between 0-3Ghz.

I welcome any helping comment. Thanks.

 

[vfone]

If your transistor model is ok, and you see that your power amplifier meets the linearity performances at 160mA, let the gate voltage 3.1V for drain current of 160mA.

 

[young.microwave.eng]

dear friend
if you have drop in voltage and current that is dramatically higher than what you expect i think it is better to check for short circuits.some times there is a small path between gate or other legs and ground

 

[xeratule]

I also have very high frequency shift. The amplifier has the expected gain at 2.2Ghz instead of 2.6Ghz and no gain at 2.6Ghz. And discordance of biasing conditions with simulation made me think of oscillation but I don't see any clue of it between 0-3 Ghz. Maybe Er of the dielectric substrate is different than I expected ( fr4 and I choosed it as 4.3) but I don't think this would effect the design that much. At least biasing condition could have been more agreeable to simulation.

I don't see any shorts between transistor legs.

 

[vfone]

Different of Er could be the reason of frequency shift, and also uncounted into the simulation of the components parasitics.

 

[xeratule]

Thanks vfone

I measure s21 and expect 10db gain at 2.6Ghz. In the simulation it shows gain above 0db between 1.6 - 3.5 Ghz. But design measurements show gain only between 2.1 - 2.2 ghz. I actually don't think the big problem comes out of only Er. There must be something else which leads to both biasing and frequency failure.

 

[vfone]

Bias would shift the impedance vs frequency, but not too much in MOS transistors.
Definitely you didn't account for all of the parasitics you have on the circuit.
For example at this frequency is very easily to place accidentally a capacitor having the SRF near operating frequency.

 

[xeratule]

So you suggest me to change the capacitances on biasing circuit?

 

[vfone]

I suggest taking into account all the parasitics you get from components, including PCB layout.

The SRF of the capacitors is the first thing you have to take in consideration at this frequency.

For example a 5.6pF 0603 capacitor have the SRF at 2.45GHz, which can give you a lot of headache placing it in a matching network.

Ideally is to use in your simulation the S-parameters of each component (passive or active, including PCB traces, pads, etc).

 

[S7_Vulcan]

For PCB Layout, try to follow the 3W rule. If the distance between two parallel RF traces is less than 3W, you will need to replace these two traces by a coupling model.

 

[xeratule]

For PCB Layout, try to follow the 3W rule. If the distance between two parallel RF traces is less than 3W, you will need to replace these two traces by a coupling model.

RF traces are far enough, thanks for the advice S7_Vulcan

vfon:

I don't have the s parameters of passive components. How can I learn SRF of those components? Or undestand if capacitors overpassed SRF and started acting inductive?

 

[vfone]

Main manufacturers of passive components (Murata, AVX, Johanson, etc) provides S parameters for their components and free software for quick component finding.