afz23
Full Member level 3
I have designed a 4GHz PLL frequency synthesizer using integer-N PLL chip.
Loop BW around 200KHz.
I have close-in phase-noise(at 100KHz offset ) of about -90dBc/Hz at PLL o/P(measured in spectrum analyzer).
I observe a residual PM 0f 0.1 radians p-p at PLL output(measured in modulation analyzer ),this value goes down to 0.02 rad if I select a LPF of 3KHz in Modulation analyzer,means some undesired frequency above 3KHz is modulating the carrier.Residual PM 0.1 radians is pretty high for a frequency synthesizer.
Experts please help, and suggest some measures to improve upon this.
Loop BW around 200KHz.
I have close-in phase-noise(at 100KHz offset ) of about -90dBc/Hz at PLL o/P(measured in spectrum analyzer).
I observe a residual PM 0f 0.1 radians p-p at PLL output(measured in modulation analyzer ),this value goes down to 0.02 rad if I select a LPF of 3KHz in Modulation analyzer,means some undesired frequency above 3KHz is modulating the carrier.Residual PM 0.1 radians is pretty high for a frequency synthesizer.
Experts please help, and suggest some measures to improve upon this.