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my 2 cents in terms of the requirements for scan-insertion.
* You have to make sure the scan clocks are properly by-passed during scanmode.
* Usually there will be functional clock, and scan-clock, if there is a scan clock going to be used for scan mode then care should be taken that the so called scan-clock should be connected to all the flops clocks properly and can be traced from the port of your module or chip from where you are going to perform scan-insertion.
* I am sure you will be using synchronizer's when there is a data transfer across clocks and for synchronizing asynchronous systems, in these scenarios you should bypass these synchronizers if you synchronize clocks or resets otherwise these outputs would not be able to reach the flip flops properly.
* latches should be made transparent during scanmode.
* Resets also should be properly bypassed and made sure that all the flops gets resetted properly and in a proper state during scan-mode.
* make sure you have a list of the flops which you dont want to insert scan for
* From the tester point of view, know your maximum scan chain length , means what is the maximum number of flip flops can be one in chain or so.
* have a list of negedge flops if wanted you may put in a single chain like that...
these are some of the points which you need to take care before inserting scan or need to take care.
Requirement/Inputs u required from design team is,
1. Whether the flops in the design netlist are scan-flop replaced or not. If not, u have to do that exercise.
2. SCAN specifications (Design team/customer may give this information.)
This includes the
a)number of scan chains to be inserted.
b) test pins information (scan ports like testmode, testenable, testin, testout, testclock etc.)
3. Ask them about any three state buffers and/or bi-directional buffers exist in the design? Check them and fix them based on requirement.
4. Ask for any macros like RAMs, ANALOG Macros etc. If exists, u have to make up ur mind for all the work to be done to handle these macros.
5. Any special requirements to be taken care during scan for this particular design.
6. Ask them about any floating nets that were supposed to fix at later stages. This is because some floating nets will draw leakage currents and chip might damage. So u will be responsible to verify for floating nets and report to them.
Rest, u will came to know automatically during the work. Good Luck
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